No-Code Power Management Cluster With Integrated Test Paths
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Solution Overview
Problem
Existing power management designs for system-on-chips (SoCs) require separate functional and test clock/reset paths, leading to inefficient design processes and lack of data testing for power elements during power-up and power-down sequences.
Innovation Solution
A no-code approach for designing a power management cluster that integrates data testing in a test mode, using a power management cluster design system with a memory, power component storage, hardware code logic, and processors to generate and connect power and data test controller instances, enabling simultaneous design of functional and test data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate functional and test clock/reset paths are used in power management design, then functional operation is ensured, but design complexity increases and resource requirements increase
Solution Approach 1:
The patent merges the functional clock/reset path and test clock/reset path into a single integrated power management cluster. The multiplexer dynamically switches between functional mode and test mode, allowing both functional operation and data testing to share the same physical paths, thereby reducing design complexity and resource requirements while maintaining reliability through mode-based separation.
Solution Approach 2:
The patent introduces dynamic mode switching capability where the power management cluster can operate in different modes (functional mode and test mode) based on control signals. The multiplexer dynamically connects different paths based on the operational mode, enabling the system to adapt between functional operation and data testing without requiring permanently separate dedicated paths.
2Reliability
If separate functional and test clock/reset paths are used, then functional reliability is maintained, but resource requirements increase
Solution Approach 1:
The power management cluster is designed with universal functionality to handle both functional operation and data testing through a single integrated structure. The multiplexer enables the same physical clock and reset paths to serve dual purposes: functional mode for normal operation and test mode for data testing, thereby reducing resource requirements while maintaining functional reliability through mode-based separation.
3Adaptability or versatility
If traditional Verilog coding approach is used for power management design, then design flexibility is achieved, but design efficiency decreases and coding complexity increases
Solution Approach 1:
The patent replaces the manual Verilog coding process with an automated code generation system. The high-level C/C++ code is automatically translated into Verilog code through a code generation tool, eliminating manual coding while preserving design flexibility. This substitution dramatically improves design efficiency and reduces coding complexity while maintaining the ability to achieve flexible power management designs through high-level abstractions.
4Adaptability or versatility
If manual Verilog coding is performed for power management design, then design customization is possible, but time consumption increases
Solution Approach 1:
The patent performs preliminary action by pre-defining power management cluster templates with standardized functionalities. These templates can be customized through high-level C/C++ code rather than manual Verilog coding. The code generation tool automatically translates these pre-defined templates into implementation code, significantly reducing time consumption while maintaining design customization capabilities through parameter configuration and template selection.
Data Source
AI summary
The present disclosure relates to a system and method for designing a power management cluster using a no-code approach, which enables data testing on power elements in a test mode. The system includes at least one processor configured to execute at least one instruction stored in a memory. The instruction includes: generating a power instance including a power management block, a power interface block, and a data controller block based on power component information; generating a data test controller instance including a test mode TDR block and a test control TDR block corresponding to the data controller block; setting a connection between the data controller block and the data test controller instance; and generating hardware code based on hardware code logic and the connection information of the power instance and the data test controller instance.