Multi-Die Interface System with NoD Network for MPU Expansion
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Solution Overview
Problem
Existing communication protocols for multi-die integration in monolithic application-specific integrated circuits are either inflexible or overly complex, making it difficult to achieve high microsystem performance while managing power consumption, and there is a need for a versatile multi-die interconnected bus protocol that meets current integrated circuit development needs in China.
Innovation Solution
An interface system for interconnected dies and MPUs, comprising an interrupt interface, DDR data interface, SPI interface, and JTAG-Core debugging interface, which enables high-speed communication and expansion by connecting these interfaces to routers for efficient data and interrupt handling, and includes a DMA control interface for managing data access between slave devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple standard protocol interfaces are integrated for multi-die integration, then the versatility and adaptability of the system is improved, but the device complexity and difficulty of interconnection increases
Solution Approach 1:
The patent implements a universal multi-die integration platform that supports multiple standard protocol interfaces (SPI, I2C, UART, CAN, LIN, FlexRay) within a single system. The NoD architecture provides a unified network layer that can handle different protocols through standardized data packets, allowing the same hardware platform to accommodate various communication standards without requiring separate dedicated interconnection systems for each protocol.
Solution Approach 2:
The patent introduces an intermediary layer consisting of the NoD network and protocol conversion circuits that mediate between different protocol interfaces. This intermediary architecture translates and routes data packets between various protocols and the core processing units, simplifying the interconnection complexity by providing a standardized mediation layer rather than requiring direct point-to-point connections between all protocol interfaces.
2Speed
If high-speed communication interfaces are implemented for data transmission, then the communication speed and data transmission rate is improved, but the power consumption increases
Solution Approach 1:
The patent implements periodic action through the use of packet-based communication where data transmission occurs in discrete bursts rather than continuous streams. The NoD network uses scheduled data packet transmission with idle periods between active communication phases, allowing the system to achieve high communication speeds during data transfer while reducing overall power consumption during idle periods. The clock management circuits also implement periodic clocking schemes that can be adjusted based on activity levels.
3Adaptability or versatility
If multiple interface types are integrated for expanding master device functionality, then the expansion capability and functionality is improved, but the address mapping complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the address space into distinct segments, each dedicated to specific interface types or functional blocks. The NoD network architecture segments the system into master devices, slave devices, and network nodes, with each segment having its own address range. This segmentation allows multiple interface types to be integrated without creating complex cross-addressing scenarios, as each interface operates within its designated address segment.
Solution Approach 2:
The patent uses the NoD network as an intermediary that handles address mapping between different interface types. Rather than requiring direct address translation between all possible interface combinations, the NoD network provides a standardized addressing layer that mediates access to slave devices and peripheral components, simplifying the address mapping process for master devices with multiple interface types.
Data Source
AI summary
The invention discloses an interface system for an interconnected die and an MPU and a communication method thereof. The system comprises a data interface, an interrupt interface, and a debugging interface; the data interface comprises an SPI interface, a DDR data interface, and a DMA control interface; the interrupt interface is used for receiving an interrupt data packet from the network and parsing the interrupt data packet to obtain a pulse interrupt input required by the MPU; the debugging interface comprises a JTAG-Core debugging interface, which is used for receiving a debugging data packet from the network and translating the debugging data packet into a JTAG protocol for MPU debugging. The invention realizes the expansion of the master device MPU in the high-performance information processing microsystem and the high-speed communication between the master device and the interconnected dies.