Parallel Processing Node Activation Timing Control

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Solution Overview

Problem

In parallel processing apparatuses, the activation time is prolonged due to the sequential activation of nodes, leading to delayed system operation as the second node waits for the first node's OS activation completion.

Innovation Solution

Implementing a control unit that initiates the setting process for the second node after a predetermined time delay from the start of the setting process on the first node, aligning their activation completion timings to allow immediate OS activation of the second node once the first node is activated.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If nodes are activated at the same time, then activation process can be performed in parallel, but access to common storage concentrates causing prolonged activation time

Engineering Contradiction:
Improveactivation speedVSAvoidstorage access congestion
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies periodic action by dividing nodes into groups and activating them in sequential waves rather than all at once. The control unit activates the first group of nodes, waits for their OS activation to complete, then activates the second group. This periodic activation pattern disperses storage access congestion across different time periods while maintaining parallel processing within each group, resolving the contradiction between parallel activation speed and storage access congestion.

Inventive Principle:
Principle #19Periodic action

2Object-affected harmful factors

If nodes are activated sequentially with waiting for OS completion, then storage access congestion is avoided, but overall activation time is prolonged

Engineering Contradiction:
Improvestorage access congestionVSAvoidactivation time
Core Design Contradiction:
Object-affected harmful factorsVSLoss of time

Solution Approach 1:

The patent applies segmentation by dividing all nodes into multiple groups (first group, second group, etc.) and processing each group separately through distinct phases. Each group undergoes setting process, OS activation, and completion detection as a segment. This segmentation allows the system to avoid storage congestion within each segment while overlapping segments in time, reducing total activation time compared to strict sequential processing of all nodes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by performing the setting process on nodes before activating them. The control unit completes the setting process (preparation) for each group before initiating OS activation. This preliminary preparation ensures nodes are ready for immediate activation, reducing waiting time and preventing storage access congestion during the activation phase itself.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the second node waits for first node's OS activation completion, then proper OS loading is ensured, but activation completion timing is delayed

Engineering Contradiction:
ImproveOS activation reliabilityVSAvoidactivation completion time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies periodic action by implementing repeated cycles of activation for different node groups. The control unit activates the first group, detects OS activation completion, then activates the second group in the next cycle. This periodic pattern ensures each group receives proper OS activation attention (maintaining reliability) while the overall system achieves faster activation completion through parallel group processing across cycles.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS11487553B2Parallel processing apparatus of controlling node activation timing, node activation method of controlling node activation timing, and non-transitory computer-readable storage medium for storing program of controlling node activation timing
Publication Date: 2022.11.01 FUJITSU LTD
  • US11487553B2 patent drawing
  • US11487553B2 patent drawing
  • US11487553B2 patent drawing

AI summary

A parallel processing apparatus includes: a first node including a storage unit that stores a program, the first node being activated when the program loaded from the storage unit is executed; a second node activated when the program loaded from the storage unit of the first node is executed; and a control unit configured to execute a setting process for setting a state where the program may be loaded to each of the first node and the second node, wherein the control unit starts the setting process on the second node after a predetermined time elapses since start of the setting process on the first node, and wherein the predetermined time is a time at which an activation completion timing of the first node is aligned with a completion timing of the setting process on the second node.