Node Contact Structure Filling for Gap-Free Semiconductor Memory
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Solution Overview
Problem
The manufacturing of Node Contact (NC) structures in semiconductors often results in gaps due to the narrow and long nature of NC holes, leading to degradation of electrical properties during polysilicon filling.
Innovation Solution
The method involves forming bit line contact mask structures above active areas, performing downward etching to create node contact holes, and filling them with semiconductor material to form first and second node contact structures, avoiding subsequent deepening and lateral etching to prevent gap formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the NC hole is made narrow and long to achieve precise node contact formation, then the contact precision is improved, but gaps are easily generated during polysilicon filling, deteriorating electrical properties
Solution Approach 1:
The patent divides the polysilicon filling process into two separate stages: first filling the NC hole to form the first node contact structure, then filling the gap between bit line structures to form the second node contact structure. This segmentation prevents gap formation by ensuring the NC hole is filled before subsequent etching and filling operations that could create voids.
Solution Approach 2:
The patent performs preliminary filling of the NC hole with polysilicon before forming the bit line structures and before performing lateral etching. This preliminary action ensures that the narrow NC hole is completely filled with conductive material before any operations that might create gaps, thereby maintaining electrical reliability.
2Length of stationary object
If continuous deepening of the NC hole is performed to achieve proper contact depth, then the contact depth is improved, but the process complexity and time consumption increase
Solution Approach 1:
The patent performs preliminary etching to form the NC hole to the required depth before forming the bit line structures. This preliminary action establishes the correct contact depth early in the process, eliminating the need for subsequent deepening operations and improving manufacturing efficiency.
Solution Approach 2:
The patent separates the etching process into distinct stages: first etching the NC hole to the target depth, then forming bit line structures, and finally performing lateral etching. This segmentation allows each operation to be optimized independently, reducing overall process complexity and time consumption.
3Manufacturing precision
If lateral etching is performed after polysilicon filling to adjust the NC structure shape, then the structural precision is improved, but gaps are generated, deteriorating electrical properties
Solution Approach 1:
The patent segments the structure formation process so that the NC hole is completely filled with polysilicon before any lateral etching of bit line structures occurs. This segmentation ensures that the fill operation is completed while the hole is still accessible, preventing gap formation that would occur if etching were performed first.
Solution Approach 2:
The patent performs preliminary filling of the NC hole with polysilicon before performing lateral etching operations on the bit line structures. This preliminary filling action ensures that the narrow NC hole is completely filled with conductive material before any operations that might create gaps, thereby maintaining electrical reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical properties of semiconductors by preventing gaps during polysilicon filling and eliminating the need for deepening operations, enhancing manufacturing efficiency.
Implementation Method 1
Downward etching is performed along the plurality of bit line contact mask structures to form a node contact hole in the active area terminal
Implementation Method 2
the node contact hole is filled with a semiconductor material to form a first node contact structure
Data Source
AI summary
A method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory are provided. The method includes: providing a substrate, the substrate including a plurality of active areas; forming bit line contact mask structures above the plurality of active areas, each bit line contact mask structure at least covering one active area terminal; performing downward etching along the bit line contact mask structures to form a node contact hole in the active area terminal, and filling the node contact hole with a semiconductor material to form a first node contact structure; and forming a plurality of bit line structures above the plurality of active areas, and continuously filling gaps between the plurality of bit line structures with the semiconductor material until a second node contact structure is formed, the first node contact structure and the second node contact structure collectively forming a node contact structure.