Computation Node Reduction with Concurrent Packet Error Checking
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Solution Overview
Problem
In large-scale computations, the error checking of packets in computation node devices is delayed due to the need to receive the entire packet before performing the check, which prolongs the waiting time for reduction operations, especially with larger packets.
Innovation Solution
A computation node device is equipped with a buffer, a receiver, and an error check circuit that performs error checks concurrently with packet reception, allowing the reduction operation to start before the error check result is received, using the data from the buffer and the packet.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the error check is performed after completely receiving the packet, then the accuracy of error detection is improved, but the waiting time before the reduction operation starts increases
Solution Approach 1:
The error check circuit performs error checking on packet data while the receiver is still receiving the packet, before the packet reception is completely finished. This preliminary error checking action overlaps with the packet reception process, allowing the reduction operation to start earlier without compromising error detection accuracy.
Solution Approach 2:
The error check circuit continuously performs error checking on incoming packet data as it is being received, rather than waiting for complete packet reception. This continuous useful action ensures that error detection proceeds without interruption and completes earlier, reducing the waiting time for the reduction operation.
2Quantity of substance
If the packet size is increased, then the data transmission capacity is improved, but the time to complete packet reception and error check increases
Solution Approach 1:
The error check circuit begins error checking on packet data while the receiver is still receiving the packet, performing the error check action in advance before packet reception completes. This allows larger packets to be processed more efficiently by overlapping error checking with the reception process.
Solution Approach 2:
The patent introduces a temporal dimension to the packet processing by performing error checking concurrently with packet reception rather than sequentially. This dimensional change in processing timing allows larger packets to be handled without proportionally increasing the total processing duration.
Data Source
AI summary
A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.