Multi-Node Shared Memory Coherence via Home Node Mediation

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Solution Overview

Problem

Existing computing systems face challenges in efficiently managing shared memory across multiple nodes, particularly in maintaining coherence and detecting violations in data modifications.

Innovation Solution

The method involves each node writing to a shared memory at each time step, with hardware-maintained coherence domains and nodes connected to each other. Modifications to the shared memory are recorded, and a hash table is used to track node identifiers, allowing for detection of violations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple nodes write to shared memory simultaneously to increase processing capacity, then productivity is improved, but coherence maintenance and violation detection become more complex

Engineering Contradiction:
Improveprocessing capacityVSAvoidcoherence management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a home node as an intermediary that manages coherence for each shared memory address. The home node acts as a mediator between multiple accessing nodes, tracking which node has write permission and coordinating memory access to maintain coherence without requiring complex peer-to-peer communication between all nodes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces complex software-based coherence protocols with hardware-enforced mechanisms. Each node includes hardware logic that automatically enforces read-only access to shared memory addresses for non-home nodes, eliminating the need for software to manually manage coherence states and reducing overall system complexity

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If nodes can modify shared memory values freely to increase flexibility, then adaptability is improved, but data integrity and coherence are compromised

Engineering Contradiction:
Improvememory access flexibilityVSAvoiddata coherence
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent implements different access permissions for different nodes based on their role. The home node has full read-write access to its managed addresses, while other nodes have read-only access. This localized differentiation of permissions allows flexible data production by the home node while ensuring data integrity through restricted access by other nodes

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent prevents potential coherence violations before they can occur by enforcing read-only access restrictions at the hardware level for non-home nodes. This preliminary prevention mechanism blocks any attempt by non-home nodes to modify shared memory addresses they don't own, ensuring data integrity without requiring continuous monitoring or validation

Inventive Principle:
Principle #9Preliminary anti-action

3Measurement precision

If a hash table is used to track node identifiers for violation detection, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improveviolation detection accuracyVSAvoidtracking structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent creates a simplified copy or representation of the memory address space in the form of a hash table that maps addresses to home node identifiers. This hash table serves as a compact lookup structure that enables precise violation detection through simple hash computations, avoiding the need for complex comparison logic across all node identifiers

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20250139007A1Systems and methods for computing with multiple nodes
Publication Date: 2025.05.01 SAMSUNG ELECTRONICS CO LTD
  • US20250139007A1 patent drawing
  • US20250139007A1 patent drawing
  • US20250139007A1 patent drawing

AI summary

Systems and methods for computing with multiple nodes. In some embodiments, a method includes writing, during each of a sequence of time steps, by each node of a plurality of nodes, to a shared memory, the shared memory being shared by the nodes, wherein: each of the nodes includes a hardware-maintained coherence domain and is connected to the other nodes, and each of the nodes includes a respective portion of the shared memory.