Noff III-Nitride HEMT Gate Segmentation for Low On-Resistance
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Solution Overview
Problem
Current manufacturing methods for Normally Off (Noff) III-Nitride High Electron Mobility Transistors (HEMTs) result in significant degradation of transistor characteristics and increased complexity, compromising channel carrier mobility and on-resistance (Ron) compared to conventional Normally-On III-N Based HEMTs.
Innovation Solution
A HEMT design featuring a source and drain with a III-N buffer and barrier layer forming a 2DEG, where the first gate electrode extends into the barrier layer to isolate the 2DEG, and a conductive structure with columns that maintain conductivity with minimal alteration, along with a second gate that ensures Noff characteristics through appropriate gate insulator material and thickness choices, reducing Ron and threshold voltage sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional complicated treatment or process steps are used to manufacture Noff III-N HEMT, then Noff characteristics are achieved, but transistor characteristics are significantly degraded and manufacturing complexity increases
Solution Approach 1:
The device is divided into two gate electrodes with distinct functions: the first gate electrode (extending into the barrier layer) provides Noff characteristics by depleting the 2DEG, while the second gate electrode maintains carrier mobility and reduces on-resistance. This segmentation allows each gate to be optimized independently, achieving Noff characteristics without the need for complicated additional processing steps that would otherwise be required.
2Reliability
If additional complicated treatment or process steps are used to manufacture Noff III-N HEMT, then Noff characteristics are achieved, but on-resistance increases due to compromised channel carrier mobility
Solution Approach 1:
By dividing the gate function into two separate electrodes, the first gate can be designed to provide Noff characteristics while the second gate is optimized to maintain high carrier mobility in the channel region. This eliminates the need for additional complicated treatments that would compromise the 2DEG quality and increase on-resistance.
Solution Approach 2:
The second gate electrode acts as an intermediary structure that mediates between the Noff requirement (first gate) and the need for high carrier mobility (channel). It provides a conductive path that maintains low on-resistance while allowing the first gate to establish the Noff characteristics through 2DEG depletion.
3Reliability
If first gate electrode extends into barrier layer to isolate 2DEG, then Noff characteristics are achieved, but manufacturing complexity increases
Solution Approach 1:
The first gate electrode is segmented to extend only into the barrier layer and not through it, creating a controlled depletion region that provides Noff characteristics. This partial extension is sufficient to isolate and deplete the 2DEG without requiring the gate to traverse the entire barrier layer thickness, thereby limiting the increase in device structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced on-resistance and improved resilience to high voltages with simpler manufacturing processes, minimizing the Ron-Vbr trade-off and allowing for robust, low-power electronic circuitry with reduced failure prone transistor performance.
Implementation Method 1
Depletion of 2DEG below the first gate provides Noff characteristics to the device
Implementation Method 2
The conductive columns may alter the conductivity of a conductive channel formed by the 2DEG
Data Source
AI summary
A High Electron Mobility Transistor comprising a source and a drain, a III-N buffer layer and a III-N barrier layer jointly forming a 2DEG in the buffer layer between the source and the drain, a first gate electrode configured to receive a gate bias voltage and a second gate electrode located between the drain and the first gate and conductively connected to the source via the 2DEG.