Noise Attenuation Wall for IC Package Crosstalk

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Solution Overview

Problem

Integrated circuit packages face challenges with crosstalk due to increased density, leading to noise interference between signals from different circuit dies within the same package, which existing solutions fail to adequately address without consuming excessive circuit platform real estate.

Innovation Solution

The implementation of a noise attenuation wall using a combination of microbumps, C4 bumps, and vias to create an isolation region that attenuates noise by coupling aggressor signals to ground, effectively reducing crosstalk between digital and analog circuitry within the same IC package.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If integrated circuit density is increased to improve productivity, then more logic features are implemented in a given size, but crosstalk and noise interference between signals increase

Engineering Contradiction:
Improvelogic densityVSAvoidcrosstalk noise
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary noise attenuation wall structure composed of microbumps, C4 bumps, and vias that acts as a mediator between digital and analog circuit dies. This wall provides a controlled impedance path to ground, intercepting noise signals before they can couple to sensitive circuits, thereby resolving the crosstalk issue while maintaining high density integration

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If noise attenuation structures are added to reduce crosstalk, then noise interference is reduced, but circuit platform real estate is consumed

Engineering Contradiction:
Improvenoise interferenceVSAvoidcircuit platform area
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent applies local quality by implementing noise attenuation features only in specific critical areas where digital and analog circuits are in close proximity. The noise attenuation wall is strategically positioned at interfaces and around high-risk signal paths, providing targeted noise shielding only where needed rather than across the entire platform, thus minimizing area consumption while maintaining effectiveness

Inventive Principle:
Principle #3Local quality

3Productivity

If multiple circuit dies are integrated in the same package to improve productivity, then more functionality is achieved, but opportunities for signal interference increase

Engineering Contradiction:
Improvepackage functionalityVSAvoidsignal interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the multi-die package into distinct noise zones by implementing noise attenuation walls that physically and electrically separate digital and analog die regions. The segmentation is achieved through distributed microbumps and C4 bumps that create isolated ground domains, preventing noise propagation between different functional blocks while maintaining system-level integration

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively reduces noise interference between different types of circuitry, allowing for more efficient use of circuit platform space by providing targeted noise shielding, thereby enhancing the overall performance of integrated circuit packages.

Implementation Method 1

coupling aggressor signals to ground

Methodology Applied
Scientific EffectGround coupling: Earthing

Implementation Method 2

using a combination of microbumps, C4 bumps, and vias to create an isolation region

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentEP2901478B1Noise attenuation wall
Publication Date: 2018.10.10 XILINX INC
  • EP2901478B1 patent drawingFigure 1
  • EP2901478B1 patent drawingFigure 2-1
  • EP2901478B1 patent drawingFigure 2-2

AI summary

An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer (203) has first vias (211). First interconnects (205) and second interconnects (206) respectively are coupled on opposite surfaces of the interposer (203). A first portion of the first interconnects (205) and a second portion of the first interconnects (205) are spaced apart from one another defining an isolation region (220) between them. A substrate (204) has second vias (212). Third interconnects (207) and the second interconnects (206) are respectively coupled on opposite surfaces of the package substrate (204). A first portion of the first vias (211) and a first portion of the second vias (212) are both in the isolation region (220) and are coupled to one another with a first portion of the second interconnects (206).