Noise Filter Circuit Layout for ESL Cancellation and Line Balance
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Solution Overview
Problem
Existing noise filter circuits using ESL cancellation structures are not suitable for line-to-line capacitors, as they degrade the balance between lines and are difficult to implement on double printed substrates with single-layer dielectric layers.
Innovation Solution
A noise filter circuit design featuring two sets of coupling loops on both the positive and negative electrode paths, with capacitors connected between these paths, allows for ESL cancellation without degrading the balance between lines and can be applied to double printed substrates, using a single-layer dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an ESL cancellation structure is used for a line-to-line capacitor, then the ESL is canceled, but an inductor is added to one of the two main lines due to mutual induction which degrades the balance between lines
Solution Approach 1:
The patent applies asymmetry by intentionally introducing a compensating inductor with opposite polarity to the mutual inductance generated by the ESL cancellation structure. This compensating inductor is connected in series with one of the main lines to counterbalance the inductive effect, thereby restoring symmetry and balance between the two main lines while maintaining ESL cancellation functionality.
2Ease of manufacture
If a multilayer substrate is used for the ESL cancellation structure, then the structure can be implemented, but it is difficult to use for a double printed substrate whose dielectric layer is a single layer
Solution Approach 1:
The patent achieves universality by designing the ESL cancellation structure with loop lines that can be effectively implemented on both multilayer substrates and double printed substrates with single-layer dielectric layers. The loop line configuration uses planar routing patterns that are compatible with standard PCB manufacturing processes, allowing the same design to be manufactured on different substrate types without requiring complex three-dimensional wiring or additional layers.
3Reliability
If the ESL cancellation structure is used, then filter performance degradation is reduced, but the device complexity increases due to additional loop lines and capacitors
Solution Approach 1:
The patent applies merging by integrating the ESL cancellation function directly into the existing filter circuit topology. The loop lines are routed to follow the natural signal paths between the capacitor terminals and the main lines, combining the ESL cancellation functionality with the filter structure rather than adding separate, independent cancellation circuits. This integration reduces overall device complexity while maintaining filter performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively cancels ESL in line-to-line capacitors, reduces filter performance degradation, and maintains line balance, while being cost-effective by using a double printed substrate instead of multilayer substrates.
Implementation Method 1
the first inductor and the second inductor are arranged to generate mutual induction such that the inductance thereof and the inductance of a parasitic inductor in the grounding line are the same in the magnitude and inverse to each other
Data Source
AI summary
A positive electrode side input loop line (10a) and a positive electrode side output loop line (10b), and a negative electrode side input loop line (11a) and a negative electrode side output loop line (11b) form two sets of coupling loops, and the loop lines of the two sets have the same winding direction, and have the same loop sizes of and relative relationship between the loop lines. A capacitor (3) is connected in series between the positive electrode side input loop line (10a) and the negative electrode side input loop line (11a).