Image Signal Noise Reduction Shared Memory Architecture
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Solution Overview
Problem
Existing noise reduction apparatuses in image processing require multiple dedicated memory devices and sequential noise filtering circuits, leading to increased manufacturing costs and memory bandwidth burdens.
Innovation Solution
A noise reduction apparatus with detecting logic for multiple noise characteristics and corresponding filtering processes, allowing for pixel-by-pixel noise detection and flexible output selection to reduce memory usage and bandwidth demands, incorporating a selecting unit or computing unit to determine the appropriate filtered signal for output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dedicated memory devices are used for each noise filtering stage, then the noise filtering process can be performed sequentially and reliably, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple dedicated memory devices into a single shared memory device that is reused across different noise filtering stages. The memory device stores video data and is accessed by impulse noise filtering, spatial noise filtering, and temporal noise filtering circuits sequentially, eliminating the need for separate memory devices at each stage and thereby reducing manufacturing costs while maintaining reliable operation.
Solution Approach 2:
The shared memory device is designed to serve multiple functions across different filtering stages. It stores video data for impulse noise detection, spatial noise filtering, and temporal noise filtering operations, making a single memory device universal for all noise reduction processes rather than requiring dedicated memory for each function.
2Ease of manufacture
If a shared memory device is used for all noise filtering stages, then manufacturing cost is reduced, but the memory bus bandwidth becomes heavily burdened due to repetitive access
Solution Approach 1:
The patent segments the noise filtering process into distinct stages (impulse noise filtering, spatial noise filtering, temporal noise filtering) that sequentially access the shared memory device. Each stage performs its specific filtering operation and writes results back to the same memory device, allowing the memory bus to handle traffic in an organized sequential manner rather than simultaneous competing accesses, thereby managing bandwidth burden effectively.
3Reliability
If sequential noise filtering is performed with individual computing units, then each noise type can be processed independently and reliably, but the device complexity increases
Solution Approach 1:
The patent combines multiple computing units into a single integrated noise reduction apparatus that performs sequential noise filtering. The apparatus includes detection logic and filtering circuits that work together in sequence within one device, eliminating the need for separate independent computing units for each noise type while maintaining reliable independent processing through sequential operation and shared memory.
Data Source
AI summary
The present invention provides a noise reduction apparatus and method thereof. The noise reduction apparatus includes a first detecting logic, a second detecting logic, a first noise filtering logic, a second noise filtering logic, and an output logic. The first detecting logic detects if a video signal has a first noise characteristic. The second detecting logic detects if the video signal has a second noise characteristic. The first noise filtering logic performs a first noise filtering process upon the video signal to generate a first filtered signal. The second noise filtering logic performs a second noise filtering process upon the video signal to generate a second filtered signal. The output logic receives the first filtered signal and the second filtered signal, and references detection results provided by the first detecting logic and the second detecting logic when generating an output signal.