Noise-Shaped Sample Rate Conversion With Elastic FIFO Buffering
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Solution Overview
Problem
Existing digital sample rate converters for radio frequency signals introduce phase noise and require complex digital phase lock loops, leading to increased power consumption and reduced robustness, especially when dealing with asynchronously varying clock rates.
Innovation Solution
The implementation of an elastic storage element, low-pass filter, and delta-sigma modulator in conjunction with a modulo-N counter, which absorbs sample rate variations and adjusts the sample rate without the need for a digital phase lock loop, thereby reducing phase noise and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a digital phase lock loop is used to convert sample rates, then sample rate conversion can be achieved, but phase noise is introduced and power consumption increases
Solution Approach 1:
The patent removes the digital phase lock loop from the sample rate conversion architecture, extracting the harmful phase noise generation mechanism while retaining the essential sample rate conversion functionality through a simplified elastic buffer-based approach
Solution Approach 2:
The patent converts the harmful phase noise issue into a benefit by using noise shaping to push quantization noise out of the signal band and into adjacent bands where it can be filtered, thereby achieving sample rate conversion without introducing in-band phase noise
2Speed
If a digital phase lock loop is used to convert sample rates, then sample rate conversion can be achieved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the complex digital phase lock loop architecture, replacing it with a simpler elastic buffer and counter mechanism that achieves the same sample rate conversion function with significantly reduced complexity
Solution Approach 2:
The patent segments the sample rate conversion function into independent elastic buffers for different clock domains, allowing each buffer to operate autonomously and simplifying the overall control architecture compared to a monolithic phase lock loop
3Speed
If a digital phase lock loop is used to convert sample rates, then sample rate conversion can be achieved, but power consumption increases
Solution Approach 1:
The patent removes the power-hungry digital phase lock loop from the architecture, replacing it with lower-power elastic buffers and counters that consume significantly less energy while maintaining sample rate conversion functionality
Solution Approach 2:
The elastic buffers automatically adapt to clock rate variations without requiring complex control logic, allowing the system to self-regulate sample rate conversion with minimal power consumption
4Speed
If a digital phase lock loop is used to convert sample rates, then sample rate conversion can be achieved, but robustness decreases
Solution Approach 1:
The patent removes the digital phase lock loop, which is susceptible to noise and instability, replacing it with robust elastic buffers that are inherently more reliable in handling asynchronous clock domains
Solution Approach 2:
The patent uses elastic buffers to pre-absorb and cushion clock rate variations and jitter before they can propagate through the system, enhancing robustness against timing uncertainties and clock domain mismatches
Data Source
AI summary
Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.