Noise-Tolerant Clock Circuit Using Compensation and Comparison
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Solution Overview
Problem
Existing clock circuits in integrated circuits are complex and costly due to their need to address variations in temperature, ground noise, and power noise, often requiring significant die area and power consumption to generate a uniform output clock signal.
Innovation Solution
A clock integrated circuit that includes a compensation circuit, timing circuitry, and comparison circuitry, where the compensation circuit generates a compensated voltage reference to mitigate variations in supply voltage and temperature, allowing for the omission of other circuitry and reducing complexity and cost, with the timing circuitry alternating between reference signals at a rate determined by a time constant and compared against the compensated voltage reference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffer circuits with active loads, independent bias circuitry, and bias circuitry are added to decouple power fluctuations from the clock signal, then the clock signal becomes more tolerant to power noise, but the die area and cost increase significantly
Solution Approach 1:
The patent extracts and eliminates unnecessary circuit elements (buffer circuits with active loads, independent bias circuitry) that were previously thought to be required for power noise tolerance. By taking out these redundant components, the design achieves the same reliability goal with significantly reduced die area.
Solution Approach 2:
The clock circuit is designed to be self-sufficient regarding power noise tolerance. The inherent properties of the clock circuit components and their configuration provide natural immunity to power fluctuations, eliminating the need for separate compensation circuits. The circuit serves its own noise tolerance needs without external assistance.
2Reliability
If voltage pump circuitry and voltage regulator are used to generate a reference signal, then the clock circuit becomes more stable against variations, but the layout area and current consumption increase greatly
Solution Approach 1:
The patent removes voltage pump circuitry and voltage regulator components from the clock circuit design. By extracting these high-power components, the design achieves stability through simpler, lower-power alternative mechanisms that are inherently more efficient.
Solution Approach 2:
The patent replaces expensive, high-power voltage regulation components with simpler, lower-cost circuit elements that consume minimal current. The design uses inexpensive circuit configurations that provide adequate stability without the overhead of complex voltage pumping and regulation infrastructure.
3Reliability
If voltage pump circuitry and voltage regulator are used to generate a reference signal, then the clock circuit becomes more stable against variations, but the layout area increases
Solution Approach 1:
The patent extracts and eliminates voltage pump circuitry and voltage regulator components that occupy significant layout area. By removing these bulky components, the design achieves stability through compact alternative approaches that require minimal space.
Solution Approach 2:
The patent merges the functions of voltage regulation and reference signal generation into the existing clock circuit infrastructure. By combining multiple functions into unified circuit blocks, the design eliminates the need for separate voltage pump and regulator sections, thereby reducing overall layout area while maintaining stability.
4Reliability
If complicated buffer circuits are used to isolate power fluctuations from the clock circuit, then the clock signal becomes more uniform, but the device complexity and cost increase
Solution Approach 1:
The patent removes complicated buffer circuits with active loads and independent bias circuitry from the design. By taking out these complex isolation components, the design achieves uniform clock signals through simpler, more straightforward circuit configurations that are easier to manufacture and less costly.
Solution Approach 2:
Instead of adding complex buffer circuits to isolate power fluctuations, the patent inverts the approach by designing the clock circuit to inherently reject power noise through its fundamental configuration. The design works backwards from the problem by making the clock circuit itself noise-immune rather than protecting it with additional isolation layers.
Data Source
AI summary
The clock circuit of an integrated circuit operates with tolerance of variation in power. A compensation circuit is powered by a supply voltage. The compensation circuit generates a compensated voltage reference, which is compensated for variation in the supply voltage. The compensated voltage reference is compared by comparison circuitry against an output of timing circuitry, to determine timing of the clock signal.