Non-Adjacent Memory Routing via Passthrough Channels
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Solution Overview
Problem
Existing shared memory subsystems face challenges in efficiently routing packet data across a large number of initiators, leading to increased latency and data traffic congestion.
Innovation Solution
A memory array circuit with a plurality of memory devices arranged in rows and columns, featuring passthrough channels connecting non-adjacent memory devices, and a packet router that determines routing directions and selectively forwards packets through these channels based on destination addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If packets are routed through adjacent memory devices in a mesh network, then routing is simpler, but latency increases and data traffic congestion occurs
Solution Approach 1:
The mesh network is segmented into multiple routing domains with designated border routers. Packets are routed through non-adjacent nodes by segmenting the traditional adjacent-hop routing path, allowing simultaneous transmissions and reducing congestion while maintaining manageable routing complexity through domain boundaries.
Solution Approach 2:
Border routers act as intermediaries that manage traffic between different routing domains. These intermediary nodes coordinate non-adjacent routing paths, enabling packets to skip intermediate nodes and reduce latency while the border routers maintain overall network management and routing complexity control.
2Reliability
If buffer sizes are increased to handle data traffic congestion, then data loss is reduced, but memory resource consumption increases
Solution Approach 1:
The patent extracts the congestion management function from traditional large buffers by implementing selective non-adjacent routing. This removes the need for excessive buffering by taking out the congestion problem from the memory subsystem and solving it at the routing level, thereby reducing buffer memory requirements while maintaining data delivery reliability.
Solution Approach 2:
The routing system performs preliminary action by proactively selecting non-adjacent paths before congestion occurs. By anticipating and preventing congestion through intelligent routing selection rather than reacting with large buffers, the system maintains reliability without requiring excessive memory resources.
3Speed
If non-adjacent memory devices are connected via passthrough channels, then latency is reduced, but interconnect complexity increases
Solution Approach 1:
Passthrough channels are designed with multi-functionality to reduce interconnect complexity. The same physical channel infrastructure supports both traditional adjacent routing and new non-adjacent routing paths, making the interconnect structure universal and avoiding the need for separate dedicated channels for each routing type.
Solution Approach 2:
The interconnect structure employs dynamic routing capabilities where passthrough channels can be selectively activated based on traffic conditions and destination requirements. This dynamic approach allows the system to achieve high-speed non-adjacent routing when needed while falling back to simpler adjacent routing otherwise, effectively managing interconnect complexity.
Data Source
AI summary
A memory array circuit routes packet data to a destination within the array. The memory array includes memory devices arranged in a plurality of rows and columns, as well as passthrough channels connecting non-adjacent memory devices. Each of the memory devices includes a memory configured to store packet data, and a packet router configured to interface with at least one adjacent memory device of the memory array. The packet router determines a destination address for a packet, and, based on the destination address, selectively forwards the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels. A memory interface routes the packet from a source to the memory array, and selectively forwarding the packet to one of the plurality of memory devices based on the destination address.