Non-Aligned Data Striping for Multi-Chip Memory Capacity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional data striping methods in multi-chip low-latency random read memory devices lead to a rapid reduction in usable storage capacity due to the declaration of entire rows of erase units as defective, even if only one unit is faulty, resulting in inefficient use of storage capacity.
Innovation Solution
Implementing non-aligned data striping by maintaining reserve erase units and remapping defective units to these reserves, allowing data to be striped across multiple chips without declaring entire rows defective, thus preserving storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If aligned data striping is used across multiple chips, then data access speed is improved through parallel processing, but usable storage capacity rapidly decreases due to declaration of entire rows of erase units as defective
Solution Approach 1:
The patent segments the storage device into multiple independent chips, each with its own erase units. When a defective erase unit is detected in one chip, only that specific unit is marked defective rather than the entire row across all chips. This segmentation allows functional erase units in other chips to remain usable, preserving storage capacity while maintaining parallel data access across chips for high speed performance
Solution Approach 2:
The patent applies local quality by treating each chip's erase units independently rather than uniformly across all chips. Each erase unit is evaluated on its own functionality, allowing localized defects to be isolated without affecting the quality status of erase units in other chips. This enables the system to maintain high storage capacity by preserving locally functional units while achieving high data access speed through parallel operations across chips with different local quality states
2Device complexity
If conventional aligned striping is implemented, then mapping complexity is reduced, but storage capacity is wasted due to premature declaration of functional erase units as defective
Solution Approach 1:
The patent segments the address mapping into chip-level and erase unit-level components. The mapping process first identifies the target chip, then maps to specific erase units within that chip independently. This segmentation simplifies the mapping logic compared to system-wide aligned striping, while simultaneously preventing capacity waste by allowing non-defective erase units in other chips to remain available for storage operations
Solution Approach 2:
The patent changes the mapping parameter granularity from row-level (affecting multiple chips) to erase unit-level (individual units within chips). This parameter change enables the system to maintain relatively simple mapping procedures while dramatically improving storage capacity utilization, as defective units are identified and isolated at the finest granularity level rather than at the coarser row level that affects multiple functional units across chips
Data Source
AI summary
Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.