Non-Architected Buffer for Register-Heavy Memory Moves
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Solution Overview
Problem
In RISC processor architectures, memory moves consume architected registers for an extended duration, leading to inefficiencies and decreased performance due to the need for load-store instruction pairs, which limits the availability of these scarce resources for other instructions.
Innovation Solution
Implementing copy and paste functionality within the processor core, where a copy-type request transfers data to a non-architected buffer and a paste-type request writes from this buffer to a memory-mapped device, reducing the reliance on architected registers and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load-store instruction pairs are used to move data in RISC architecture, then data movement between memory and registers is achieved, but architected registers are occupied for extended duration reducing throughput
Solution Approach 1:
The patent introduces a non-architected buffer as an intermediary component between system memory and the processor core's architected registers. This buffer serves as a temporary storage location that decouples the memory move operation from the register file, allowing data to be transferred without occupying scarce architected register resources for extended periods. The buffer acts as a mediator that absorbs the temporal burden of data movement operations.
Solution Approach 2:
The patent extracts the temporary storage function from the architected register file and relocates it to a separate non-architected buffer. By removing this intermediate storage requirement from the register subsystem, the patent allows architected registers to be released sooner, thereby increasing their availability for other instructions and improving overall processor throughput.
2Ease of operation
If architected registers are allocated for memory move operations, then data can be transferred between memory locations, but the scarce register resources become unavailable for other instructions
Solution Approach 1:
The non-architected buffer serves as a mediator that handles the temporary storage burden of memory move operations, allowing architected registers to remain available for other instructions. This intermediary component preserves the ease of memory move operations while protecting the quantity of available architected registers.
Solution Approach 2:
The patent implements a copy buffer that temporarily holds data during memory move operations. Instead of requiring architected registers to hold data throughout the entire move operation, the data is copied to and from the non-architected buffer, which has sufficient capacity to handle the temporary storage needs without consuming limited register resources.
Data Source
AI summary
A data processing system includes a processor core having a store-in lower level cache, a memory controller, a memory-mapped device, and an interconnect fabric communicatively coupling the lower level cache and the memory-mapped device. In response to a first instruction in the processor core, a copy-type request specifying a source real address is transmitted to the lower level cache. In response to a second instruction in the processor core, a paste-type request specifying a destination real address associated with the memory-mapped device is transmitted to the lower level cache. In response to receipt of the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to receipt of the paste-type request, the lower level cache issues on the interconnect fabric a command that writes the data granule from the non-architected buffer to the memory-mapped device.