Non-Binary Decoder Logic for Lower-Complexity Array Addressing
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Solution Overview
Problem
Existing decoder architectures for large electronic arrays are prone to sequential line failures due to complexity and high component count, which affects yield and integration, especially in applications like displays and sensors where minimizing failure regions is crucial.
Innovation Solution
A decoder architecture with reduced complexity is introduced, utilizing fewer inputs per logic stage by modifying the clock signal duty cycle to non-binary, allowing for fewer components and transistors, thereby reducing the risk of failures and increasing production yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional decoder architectures are used to address large electronic arrays, then the ability to eliminate sequential line failures is improved, but the circuit complexity and component count increase significantly
Solution Approach 1:
The patent changes the fundamental parameter of clock signal duty cycle from binary (50%) to non-binary values, enabling a simplified decoder architecture that uses fewer logic inputs per stage while maintaining the ability to independently address array lines without sequential failure propagation
Solution Approach 2:
The decoder is segmented into multiple independent logic stages, each with reduced input requirements. This segmentation allows the system to maintain failure independence across array lines while reducing the complexity burden on any single logic stage
2Device complexity
If shift register circuits are used for addressing, then the component count and area occupied are reduced, but the risk of consecutive line failures increases
Solution Approach 1:
By changing the clock signal duty cycle parameter to non-binary values, the invention creates a decoder architecture that achieves shift register-like simplicity in component count while incorporating independent logic stages that prevent consecutive line failures, thus combining the advantages of both approaches
3Ease of manufacture
If decoder circuits are integrated on the same substrate as large area arrays, then the number of interconnections to external components is reduced, but the manufacturing yield decreases due to complexity
Solution Approach 1:
The non-binary duty cycle parameter change enables a decoder design with reduced logic inputs per stage, directly lowering circuit complexity and improving manufacturing yield while maintaining integration capability on the same substrate as large area arrays
Solution Approach 2:
Segmenting the decoder into multiple independent logic stages with reduced inputs each facilitates better integration on substrate while improving yield by reducing the overall complexity burden
Data Source
AI summary
A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log2X inputs for receiving the clock signal inputs.