Non-Bit Aligned Event Group Test Masks for RTOS Logical Operations
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Solution Overview
Problem
Real-time operating systems (RTOS) are limited in performing complex logical operations beyond simple AND and OR computations using a single multi-bit block, as existing solutions like Narayan's mask decoder circuit and Adkisson's increment/decrement circuit do not allow embedding operations within a multi-bit block effectively.
Innovation Solution
A system and method that enables compound logical tests using a non-aligned event group test mask, where the test mask encodes operations through predefined bit patterns and spacer bits, allowing for more complex logical operations like AND-OR tests within a single test mask, even if it lacks bitwise alignment with the event group bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If simple AND and OR computations are used for event group testing, then the operation is simple and fast, but the functional capability is limited
Solution Approach 1:
The test mask is segmented into multiple functional fields: compound logical test indicator field, first logical test type indicator field, second logical test type indicator field, and test mask bits. This segmentation allows each field to perform a specific function while collectively enabling complex logical operations beyond simple AND and OR computations.
Solution Approach 2:
The patent adds dimensional complexity to the test mask structure by introducing multiple indicator fields that encode different logical test types. Instead of using a single-bit mask, the system uses a multi-field structure where each field contributes to the overall logical operation capability, enabling compound logical tests through bit pattern combinations.
2Speed
If a clock cycle is used to select submasks in a mask decoder circuit, then the mask filtering is regular and systematic, but the operation speed is limited by the clock cycle
Solution Approach 1:
The system performs self-service by using the test mask bits themselves to perform the logical testing against event group bits. The RTOS kernel directly executes the compound logical test using the encoded test mask structure without requiring an external decoder circuit to interpret and translate the mask values, eliminating the clock cycle dependency.
Solution Approach 2:
The patent extracts the logical test functionality from a separate decoder circuit and integrates it directly into the RTOS kernel's event group testing mechanism. By removing the intermediary decoder layer, the system achieves faster processing while maintaining the systematic approach to mask filtering through the structured test mask format.
3Ease of operation
If data is realigned by copying to multiple storage locations, then the data alignment is achieved, but the memory usage and operation time increase
Solution Approach 1:
The patent uses copying of test mask bit patterns into different indicator fields to represent different logical test types. Instead of copying event group data to multiple storage locations for alignment, the system copies and reuses the test mask structure itself to encode multiple test configurations, achieving operational flexibility without additional memory access overhead.
Data Source
AI summary
An operating system uses non-bit aligned test masks to encode compound logical tests within the test mask. Generally, a bit within the test mask will indicate whether the test mask is a bit-aligned test mask or a non-bit-aligned test mask. If the system detects that the test mask in a non-bit-aligned test mask, the system will traverse the test mask to extract bit-aligned sub-masks and perform multi-level logical tests with the bit-aligned sub-masks. Such a system is particularly useful when performing a compound AND-OR logical test involving mutually exclusive event group flags.