Non-blocking Cache with Integrated Reception Region
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Solution Overview
Problem
Existing data supply techniques in computer systems face challenges in reducing circuit size while maintaining processing performance, particularly due to the need for additional storage regions like fill FIFOs and cache memory, which increase circuit size and latency during cache misses.
Innovation Solution
A data supply device with a non-blocking cache mechanism that integrates the reception region within the cache memory, eliminating the need for a separate fill FIFO by using a fully associative cache with a round robin replacement method, allowing continuous processing during cache misses without temporary operation stops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a separate fill FIFO is added to implement non-blocking cache operation, then processing performance is improved by hiding refill latency, but circuit size increases due to additional storage regions
Solution Approach 1:
The patent merges the fill FIFO function with the cache memory by integrating the reception region (fill buffer) directly into the cache memory structure. This allows the cache to perform both caching and refill buffering functions simultaneously, eliminating the need for a separate fill FIFO while maintaining non-blocking operation capability.
Solution Approach 2:
The cache memory is designed to serve multiple functions: it acts as both the main cache storage and the fill buffer for incoming refill data. The reception region within the cache memory can temporarily store refill data while the cache line is being updated, enabling the cache to handle refill operations without blocking processor access.
2Loss of time
If a separate fill FIFO is implemented for non-blocking operation, then refill latency is hidden, but the number of access times to storage increases due to additional data movement
Solution Approach 1:
By combining the fill FIFO functionality with the cache memory structure, the patent eliminates the need for separate data movement between fill FIFO and cache memory. Refill data is written directly to the reception region within the cache memory, reducing the number of access operations required during refill.
Solution Approach 2:
The patent extracts the fill FIFO as a distinct component and integrates its functionality directly into the cache memory's reception region. This eliminates the intermediate storage step and reduces access overhead while maintaining the ability to hide refill latency from the processor.
Data Source
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AI summary
A data supply device includes an output unit, a fetch unit including a storage region for storing data and configured to supply data stored in the storage region to the output unit, and a prefetch unit configured to request, from an external device, data to be transmitted to the output unit, wherein the fetch unit is configured to store data received from the external device in a reception region, which is a portion of the storage region, and, according to a request from the prefetch unit, to assign, as a transmission region, the reception region where data corresponding to the request is stored, and wherein the output unit is configured to output data stored in the region assigned as the transmission region by the fetch unit.