Non-blocking Fabric SSD Controller Architecture
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Solution Overview
Problem
Traditional Solid State Drives (SSDs) face challenges in achieving high throughput, scalability, reliability, and availability due to serial data processing and limited flexibility in handling varying data sizes and priorities, which affects performance and endurance.
Innovation Solution
The implementation of a flash-based SSD controller with a non-blocking fabric and embedded processor that uses a Flash Translation Layer, Error Correction Coding, and a flash scheduler to manage data movement and prioritize commands, enabling concurrent data processing and efficient wear leveling, garbage collection, and error detection/correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional serial data processing architecture is used in SSD, then device complexity is reduced, but throughput and performance are limited
Solution Approach 1:
The patent divides the SSD controller into multiple independent processing channels (e.g., multiple NAND flash interfaces, separate read/write channels) that can operate concurrently. This segmentation allows parallel data processing without requiring a complete architectural overhaul, thereby increasing throughput while maintaining manageable complexity.
Solution Approach 2:
The patent transitions from serial (one-dimensional) data processing to parallel multi-channel processing by adding spatial dimensionality. Multiple data paths are established simultaneously, allowing concurrent operations across different channels, which dramatically improves throughput without proportionally increasing complexity.
2Loss of time
If serial data processing is used, then device complexity is lower, but latency increases
Solution Approach 1:
The patent implements preliminary actions by pre-fetching data, pre-allocating buffers, and pre-processing commands in parallel channels before they are actually needed. This reduces waiting time and latency by having data ready in advance through concurrent preparatory operations.
Solution Approach 2:
The patent ensures continuous useful action by maintaining multiple active processing channels that can operate simultaneously without idle periods. While one channel is servicing a request, others continue processing, eliminating gaps and reducing overall latency through uninterrupted parallel operations.
3Adaptability or versatility
If traditional SSD architecture is used, then ease of manufacture is improved, but scalability is limited
Solution Approach 1:
The patent designs a universal controller architecture that can accommodate multiple NAND flash interfaces and support various flash memory types through standardized protocols and configurable parameters. This multi-functionality enables scalability to different storage capacities and configurations without requiring completely different hardware designs.
Solution Approach 2:
The patent implements dynamic configurability where the controller can adapt its operating parameters, channel allocations, and processing priorities based on the specific NAND flash devices detected during initialization. This dynamic adaptation allows the system to scale efficiently while maintaining ease of manufacture through a single flexible platform.
4Productivity
If data is stored in NAND flash blocks, then storage capacity is achieved, but write performance degrades due to erase requirements
Solution Approach 1:
The patent introduces a complex caching layer and translation mechanism that acts as an intermediary between the host and NAND flash blocks. This intermediary manages the erase requirements by buffering writes, performing wear leveling, and coordinating garbage collection in the background, thereby maintaining high write performance while handling the inherent limitations of NAND flash architecture.
Data Source
AI summary
Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory.