Non-blocking Thread Counter for Compute-Near-Memory Systems
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Solution Overview
Problem
Conventional computer architectures face performance and capacity constraints due to the time and energy required for data movement between processors and memory, limiting compute performance beyond transistor scaling.
Innovation Solution
The implementation of a compute-near-memory (CNM) system with hybrid threading processors and a custom compute fabric that allows for non-blocking external device calls, enabling threads to continue execution without waiting for responses from memory operations when the results are not needed, and maintaining data consistency through a pending no-return counter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If threads block to wait for memory operation completion, then data consistency is maintained, but thread idle time increases and processing throughput decreases
Solution Approach 1:
The system performs preliminary actions by issuing memory operations without blocking the thread, using a counter to track pending operations. The thread continues execution preliminarily while the memory operation completes in the background, resolving the contradiction by eliminating idle wait time while maintaining data consistency through the counter mechanism.
Solution Approach 2:
The pending operation counter serves as an intermediary mechanism between the thread and memory operation completion. It mediates the relationship by tracking outstanding operations and controlling thread completion, allowing threads to proceed without blocking while ensuring data consistency is maintained when operations complete.
2Productivity
If threads continue execution without waiting for memory operations, then processing throughput increases, but data consistency may be compromised
Solution Approach 1:
The system implements feedback through the pending operation counter that monitors memory operation completion status. The counter provides feedback to control thread completion, ensuring that threads only complete when all pending memory operations have finished, thus maintaining data consistency while allowing concurrent execution.
Solution Approach 2:
Threads perform preliminary execution actions without waiting for memory operation completion, but the system preliminarily establishes a counter mechanism to track pending operations. This preliminary setup enables subsequent consistency checks without blocking initial thread execution, resolving the contradiction between throughput and reliability.
3Reliability
If conventional memory access protocols are used, then data consistency is ensured, but system efficiency and compute performance are limited
Solution Approach 1:
The system dynamically adjusts thread behavior based on memory operation status using the pending operation counter. Threads can dynamically continue execution when operations are pending rather than statically blocking, and the counter dynamically tracks completion status. This dynamic approach resolves the contradiction by maintaining consistency while improving efficiency.
Solution Approach 2:
The system preliminarily issues memory operations without waiting for completion, preliminarily establishing a counter to track pending operations. This preliminary action allows the system to break from conventional blocking protocols and achieve both data consistency and improved system efficiency simultaneously.
Data Source
AI summary
Devices and techniques for non-blocking external device calls are described herein. Specifically, when a processor receives an instruction with a no-return indication from a thread for a device, the processor can increase a counter corresponding to the thread based on the no-return indication. The processor can then continue execution of the thread without waiting for a return value from the device. When a return value is received for the instruction, the processor can decrement the counter. While the counter is not zero, the processor prevents the thread from completing (exiting).