Dynamic Power Control for Non-Compute Units in Integrated Circuits
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Solution Overview
Problem
Current integrated circuit (IC) systems face challenges in reducing power consumption while maintaining performance, particularly due to latency issues and high power consumption by non-compute units during memory access.
Innovation Solution
The implementation of power management logic that dynamically adjusts the power levels of non-compute units, such as the data fabric and memory controllers, based on detected memory bandwidth and latency levels, allowing for optimized power allocation across heterogeneous workloads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-compute unit clock frequencies and voltage levels are increased to improve CPU performance state, then memory bandwidth is improved, but power consumption of non-compute units becomes unnecessarily high
Solution Approach 1:
The patent implements dynamic power management for non-compute units by introducing multiple performance states (P-states) that allow runtime adjustment of clock frequency and voltage levels. The power management unit monitors workload characteristics and transitions non-compute units between performance states to match actual bandwidth requirements, preventing unnecessary power consumption when maximum performance is not needed.
Solution Approach 2:
The patent changes operational parameters (clock frequency FCLK and voltage VCC) of non-compute units based on detected workload characteristics. By monitoring bandwidth requirements and latency sensitivity of executing workloads, the system adjusts these parameters to provide optimal performance while minimizing power consumption, rather than maintaining fixed high-performance settings.
2Productivity
If data fabric frequency is increased to provide maximum memory data transfer rate, then memory bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent introduces dynamic frequency scaling for the data fabric by implementing performance states that adjust the data fabric clock frequency based on actual memory bandwidth requirements. The power management unit monitors workload characteristics and transitions the data fabric between frequency states, providing maximum transfer rates only when needed and reducing frequency to save power during lower-demand periods.
3Productivity
If non-compute units operate at high power levels to support bandwidth-intensive workloads, then memory bandwidth is improved, but power budget available for compute units is reduced
Solution Approach 1:
The patent implements dynamic power allocation between compute and non-compute units through workload characterization. The power management unit analyzes executing workload properties and dynamically adjusts non-compute unit power levels to match actual bandwidth requirements, thereby preserving power budget for compute units during compute-intensive tasks while providing enhanced bandwidth support when memory-intensive workloads are detected.
4Loss of time
If clock frequency is increased to reduce memory access latency, then latency performance is improved, but power consumption increases
Solution Approach 1:
The patent introduces dynamic frequency scaling that adjusts clock frequency based on workload latency sensitivity. The power management unit monitors workload characteristics and increases clock frequency only when latency-sensitive workloads are detected, maintaining lower frequencies during bandwidth-intensive or compute-bound workloads where latency optimization is less critical, thereby reducing unnecessary power consumption.
Data Source
AI summary
Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on the IC, and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.