Non-coplanar encapsulated microelectronic devices with bumpless build-up layer
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Solution Overview
Problem
The microelectronic industry faces challenges in producing faster and smaller packages with numerous conductive routes, leading to bandwidth limitations, reliability issues, form factor problems, and cost concerns due to the complexity of interconnection layers and multiple device integration.
Innovation Solution
A microelectronic package design featuring non-coplanar, encapsulated devices with a bumpless build-up layer structure, where microelectronic devices of varying heights are encapsulated in a material like silica-filled epoxy, and an active surface microelectronic device is electrically connected through bond wires or solder balls, with conductive vias and traces formed to achieve efficient routing without the need for solder bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple microelectronic devices are integrated in a single package, then functionality and performance are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the package into distinct functional segments: an encapsulated substrate containing multiple microelectronic devices, a separate build-up layer structure for interconnections, and an active surface device. This segmentation allows each component to be optimized independently while simplifying the overall manufacturing process compared to integrating all functions in a single complex structure.
Solution Approach 2:
The patent transitions from planar (2D) interconnection layouts to a three-dimensional architecture where devices are stacked at different heights (non-coplanar arrangement). The build-up layer structure extends vertically to provide conductive routes between devices on the encapsulated substrate and the active surface device, enabling complex functionality without increasing planar footprint or manufacturing complexity.
2Adaptability or versatility
If numerous conductive routes are formed for power/ground and I/O signals, then connectivity and performance are improved, but manufacturing complexity and design rules become more stringent
Solution Approach 1:
The patent utilizes vertical dimension in the build-up layer structure to route conductive signals. Conductive vias and traces are formed in multiple layers extending vertically from the encapsulated substrate to the active surface device, enabling numerous conductive routes for power, ground, and I/O signals without requiring complex planar routing that would increase manufacturing difficulty.
Solution Approach 2:
The build-up layer structure acts as an intermediary between the encapsulated substrate and the active surface device. It provides a structured framework with pre-formed conductive vias and traces that simplify the connection process, eliminating the need for complex direct routing between devices and reducing manufacturing stringency.
3Reliability
If traditional ball grid array attachment structures are used, then electrical connections are achieved, but reliability and scalability are compromised
Solution Approach 1:
The patent removes the traditional ball grid array attachment structures from the design. Instead of using solder balls for both electrical connection and mechanical attachment, the invention extracts the attachment function to the encapsulated substrate structure itself, which provides mechanical support and alignment features. This eliminates the reliability issues associated with ball grid arrays while maintaining ease of manufacture through simpler attachment processes.
Data Source
AI summary
A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar). The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate.