Loosely Lock-Stepped Non-Deterministic Processor Fault Tolerance
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Solution Overview
Problem
Emerging non-deterministic processor execution in multi-processor systems makes it difficult to implement strict or even loose lock-step fault tolerance, as processors executing the same software application may not perform the same sequence of instructions due to advances like speculative execution and out-of-order processing, rendering traditional fault tolerance methods ineffective.
Innovation Solution
A computing system with multiple processors executes duplicate copies of user programs in a logical processor, using synchronization logic to manage reads and writes, handle interrupts, and ensure time consistency across processors, allowing for loosely lock-stepped execution and fault tolerance without requiring cycle-by-cycle or wall clock time synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strict lock-step execution is implemented to ensure fault tolerance, then system reliability is improved, but device complexity and difficulty of implementation increase due to phase difference control in clocking signals
Solution Approach 1:
The patent extracts the synchronization requirement from the clocking signal domain and relocates it to the software instruction domain. By using a barrier synchronization mechanism implemented in software rather than hardware clocking, the system achieves fault tolerance without requiring complex phase-synchronized clocking signals across processors.
Solution Approach 2:
The patent replaces the mechanical/electrical synchronization mechanism (phase-synchronized clocking signals) with a software-based barrier synchronization mechanism. This substitution eliminates the need for complex hardware timing control while maintaining the essential fault detection and correction capabilities.
2Productivity
If speculative execution and out-of-order processing are used to improve processor performance, then productivity is improved, but strict lock-step execution becomes impossible as processors execute instructions in different orders
Solution Approach 1:
The patent introduces dynamic barrier synchronization points that can be adaptively placed within the software code. These barriers allow processors to execute instructions out-of-order and speculatively between barrier points, while ensuring that critical synchronization points maintain consistency across all processors. This dynamic approach reconciles performance optimization with fault tolerance.
Solution Approach 2:
The patent segments the execution flow into multiple instruction regions separated by barrier synchronization points. Within each segment, processors can execute instructions independently and out-of-order to maximize performance. The barriers ensure that critical sections maintain synchronization, allowing both high productivity and reliability.
3Device complexity
If processors are allowed to execute at different wall clock times to simplify implementation, then device complexity is reduced, but maintaining synchronization becomes difficult requiring instruction counting and stalling mechanisms
Solution Approach 1:
The patent introduces barrier synchronization points as intermediary mechanisms that mediate between independent processor execution and coordinated fault tolerance. These barriers act as checkpoints where processors synchronize without requiring continuous clocking signal coordination or instruction counting, eliminating the need for stalling while maintaining synchronization where needed.
4Reliability
If continuous monitoring and comparison of processor outputs is implemented to detect computational faults, then reliability is improved, but loss of time increases due to synchronization overhead
Solution Approach 1:
The patent implements periodic barrier synchronization instead of continuous monitoring. Processors execute independently between barriers, and synchronization/fault comparison occurs only at barrier points. This periodic approach maintains reliable fault detection while minimizing synchronization overhead, as processors are not continuously stalled for comparison.
Data Source
AI summary
A method and system of loosely lock-stepped non-deterministic processors. Some exemplary embodiments may be a processor-based method comprising executing fault tolerant copies of a user program, one copy of the user program executed in a first processor performing non-deterministic execution, and a duplicate copy of the user program executing in a second processor performing non-deterministic execution, with the executing in the first processor and second processor not in cycle-by-cycle lock-stepped.