Non-Divider 2X Clock Generation for Phase-Aligned Serializers
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Solution Overview
Problem
High-speed data interfaces require phase-aligned 2× frequency clock signals for double data rate transfers, but existing solutions face challenges in ensuring reliable multi-channel phase alignment and programmable frequency with a 50% duty cycle, especially due to complexities in designing a well-balanced global reset signal for divider-based clock generators.
Innovation Solution
A multiple-channel serializer circuit with a non-divider local 2× frequency clock generator structure that uses existing multiple frequencies and phases of serializer clocks, combined with flip-flop sampling and OR gate logic to generate a programmable 50%-duty-cycle phase-aligned 2× frequency clock signal, eliminating the need for a global reset signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a divider-based clock generator is used to generate 2× frequency clock signals, then the clock frequency can be doubled, but the design complexity increases due to the need for a well-balanced global reset signal in multi-channel systems
Solution Approach 1:
The invention extracts and eliminates the problematic global reset signal requirement from the divider-based clock generation approach. By using a non-divider structure with OR gates and flip-flops, the patent removes the complex reset synchronization mechanism while maintaining the 2× frequency multiplication capability across multiple channels.
Solution Approach 2:
Instead of using a divider circuit that requires reset signals to synchronize channel phases, the invention inverts the approach by using a non-divider structure that naturally generates phase-aligned clock signals through OR gate logic and flip-flop sampling, eliminating the need for complex reset signal balancing.
2Device complexity
If a non-divider structure is used to generate 2× frequency clock signals, then the global reset signal design complexity is eliminated, but achieving reliable multi-channel phase alignment and 50% duty cycle becomes challenging
Solution Approach 1:
The invention uses flip-flop sampling circuits that capture the OR gate output signals at specific clock edges, creating a feedback mechanism that ensures phase alignment across channels. The sampled signals are re-sampled and combined through additional OR gates to maintain consistent phase relationships and 50% duty cycles without requiring global reset signals.
Solution Approach 2:
The patent employs periodic sampling actions using flip-flops triggered by rising and falling edges of clock signals. This periodic sampling of the OR gate outputs ensures that phase alignment is maintained through regular, synchronized capture events, achieving reliable multi-channel coordination without complex reset logic.
3Adaptability or versatility
If existing multiple frequencies and phases of serializer clocks are combined using flip-flop sampling and OR gate logic, then a programmable 50%-duty-cycle phase-aligned 2× frequency clock signal is generated, but the circuit structure becomes more complex
Solution Approach 1:
The non-divider clock generation circuit serves multiple functions: it multiplies frequency by 2, ensures 50% duty cycle, achieves phase alignment across channels, and provides programmable frequency selection. By combining OR gate logic with flip-flop sampling circuits, the patent creates a universal circuit structure that handles all these requirements simultaneously without needing separate dedicated circuits for each function.
4Speed
If a divider-based approach is used for clock generation, then frequency multiplication is achieved, but the data transfer efficiency is reduced due to the complexity and potential delays in global reset signal distribution
Solution Approach 1:
The non-divider circuit structure performs frequency multiplication and phase alignment in advance without requiring subsequent reset signal distribution. By generating the 2× frequency clock signals directly through OR gate logic and flip-flop sampling, the patent eliminates the time-consuming global reset signal distribution step, thereby improving data transfer efficiency while maintaining high-speed operation.
Data Source
AI summary
One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.