Non-doped Semiconductor Bit Line for DRAM Parasitic Capacitance
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Solution Overview
Problem
Conventional DRAM devices face high parasitic capacitance due to doped polysilicon/metal stack bit line structures, which also complicate the fabrication process, and replacing this with a metal bit line structure increases the gap between the cell and peripheral regions, making fabrication more difficult.
Innovation Solution
A memory device with a non-doped semiconductor layer and a method involving a substrate with word lines and isolation structures, where a non-doped semiconductor layer is formed, trenches are patterned, and a doped-material layer is filled to create contact portions aligned with or below the semiconductor layer surface, followed by a metal-stacking layer in direct contact with these portions, reducing parasitic capacitance and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a doped polysilicon/metal stack is used as a bit line structure, then the bit line structure can be formed, but high parasitic capacitance occurs due to the high height of the bit line structure
Solution Approach 1:
The patent changes the material parameter from doped polysilicon to non-doped semiconductor material, which fundamentally alters the electrical properties and reduces parasitic capacitance. This parameter change transforms the bit line structure from high-capacitance to low-capacitance while maintaining manufacturability
Solution Approach 2:
The patent employs a composite structure combining non-doped semiconductor layer with metal layers, creating a hybrid bit line structure that leverages the low parasitic capacitance property of non-doped semiconductor while maintaining the electrical conductivity benefits of metal interconnections
2Object-generated harmful factors
If a metal bit line structure is used to replace the doped polysilicon/metal stack, then parasitic capacitance is reduced, but the gap between the cell region and the peripheral region increases
Solution Approach 1:
The patent applies local quality by using non-doped semiconductor material specifically in the bit line region where low parasitic capacitance is critical, while maintaining other structural elements that facilitate integration between cell and peripheral regions. This localized material optimization reduces parasitic capacitance without necessarily increasing overall device complexity
Solution Approach 2:
The patent addresses the gap issue by extending the non-doped semiconductor layer in the vertical dimension to directly contact the metal stacking layer, creating a three-dimensional integrated structure that reduces horizontal gaps and improves connectivity between cell and peripheral regions
3Object-generated harmful factors
If a non-doped semiconductor layer is used, then parasitic capacitance is reduced, but the fabrication process complexity may increase
Solution Approach 1:
The patent applies preliminary action by forming the non-doped semiconductor layer early in the fabrication sequence, before subsequent metal layer depositions. This early formation integrates the low-parasitic-capacitance material into the base structure, allowing standard metal deposition processes to follow without requiring additional complex fabrication steps
Data Source
AI summary
A memory device including a substrate, a non-doped semiconductor layer, a plurality of contact portions and a metal-stacking layer is provided. The substrate includes a plurality of word lines and a plurality of isolation structures. The non-doped semiconductor layer is disposed on the substrate. The contact portions are adjacent to the non-doped semiconductor layer and in direct contact with the substrate. The metal-stacking layer is disposed on the substrate. A portion of the metal-stacking layer is disposed on the non-doped semiconductor layer and in direct contact with the contact portions.