Non-DRAM Memory Controller for Non-Volatile Modules
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Solution Overview
Problem
Computing systems using DRAM integrated circuits face high power consumption and require frequent refresh cycles, while non-volatile memory integrated circuits offer lower power consumption and different access performance characteristics, necessitating a solution to integrate non-DRAM memory controllers for efficient access to non-volatile memory modules.
Innovation Solution
A non-DRAM memory controller is introduced to control access to non-volatile memory modules, utilizing data communication protocols that differ from DRAM modules, and incorporating feedback status control signals to manage non-deterministic write and erase operations, allowing for efficient integration with existing DRAM systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM integrated circuits are used for main memory, then fast read and write access is achieved, but power consumption increases and frequent refresh cycles are required
Solution Approach 1:
The system is segmented into two distinct memory subsystems: a DRAM memory controller handling volatile memory operations, and a non-DRAM memory controller handling non-volatile memory operations. This segmentation allows each controller to be optimized for its specific memory type, enabling fast access when needed while reducing overall power consumption by eliminating refresh cycles for non-volatile portions.
Solution Approach 2:
The patent changes the operational parameters of the memory system by introducing non-volatile memory modules with different electrical characteristics than DRAM. These modules operate without refresh cycles and have different voltage requirements, fundamentally changing the energy consumption profile while maintaining acceptable access times through protocol optimization.
2Use of energy by moving object
If non-volatile memory integrated circuits are used, then power consumption is reduced and no refresh cycles are needed, but access performance characteristics differ from DRAM
Solution Approach 1:
A dedicated non-DRAM memory controller acts as an intermediary between the processor and non-volatile memory modules. This controller translates processor memory requests into appropriate protocols for the non-volatile memory, optimizing access patterns and timing to bridge the performance gap between DRAM and non-volatile memory while maintaining low power consumption.
Solution Approach 2:
The system changes access parameters dynamically by using different communication protocols and timing sequences when accessing non-volatile memory compared to traditional DRAM. This includes adjusted read/write cycle times, voltage levels, and control signal timing to accommodate the different electrical characteristics of non-volatile memory while achieving acceptable performance.
3Productivity
If a non-DRAM memory controller is introduced to control non-volatile memory modules, then efficient access to non-volatile memory is achieved, but device complexity increases
Solution Approach 1:
The non-DRAM memory controller is designed with universal interfaces that can work with multiple types of non-volatile memory technologies (Flash, EEPROM, MRAM, etc.). This multi-functionality allows a single controller architecture to handle different memory types through standardized protocols, reducing overall system complexity despite the added capability to manage non-volatile memory.
Solution Approach 2:
The memory controller implements feedback mechanisms that monitor memory module status and dynamically adjust access patterns. This feedback system optimizes performance by adapting to the actual state of non-volatile memory modules, improving access efficiency while maintaining manageable complexity through intelligent control rather than hardware complexity.
4Quantity of substance
If non-volatile memory modules are integrated into existing DRAM systems, then memory capacity is enhanced and power is conserved, but compatibility with existing DRAM protocols must be maintained
Solution Approach 1:
The non-DRAM memory controller serves as an intermediary layer between the existing DRAM system infrastructure and the new non-volatile memory modules. It translates standard memory bus protocols into appropriate commands for non-volatile memory, allowing seamless integration without requiring changes to the existing DRAM controller or system software, thus maintaining protocol compatibility while enhancing capacity.
Solution Approach 2:
The system achieves universal compatibility by designing the non-DRAM memory controller to speak both the traditional DRAM protocol language and the native protocol of various non-volatile memory types. This dual-language capability allows the system to maintain compatibility with existing DRAM infrastructure while supporting multiple non-volatile memory technologies for enhanced capacity and reduced power consumption.
Data Source
AI summary
A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.