Non-Gated Well Tap Cell Layout for Controlled FinFET Source/Drain Growth
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Solution Overview
Problem
Existing guard ring structures in integrated circuits face issues such as increased size and manufacturing risks due to dummy gates, which constrain source/drain formation and lead to high gate density, CMP dishing, and erosion.
Innovation Solution
The integration of a well tap cell surrounding IC cells, which is free of gate structures and uses a hard mask to define source/drain regions through etching and epitaxial growth, reducing gate density and allowing for a smaller well tap cell size, thereby minimizing manufacturing risks and increasing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gates are used to constrain source/drain formation, then source/drain formation is controlled, but gate density increases and manufacturing risk increases
Solution Approach 1:
The patent removes dummy gates from the guard ring structure, extracting the problematic element that caused high gate density and manufacturing risk. The guard ring is redesigned to function without gates, using only source/drain regions and isolation structures to achieve the same protective function with lower complexity.
Solution Approach 2:
The patent uses a simplified guard ring structure that relies on temporary or non-critical gate-like structures only where absolutely necessary, rather than uniformly applying dummy gates throughout. This reduces overall gate density while maintaining sufficient source/drain formation control in critical areas.
2Manufacturing precision
If dummy gates are used to constrain source/drain formation, then source/drain formation is controlled, but CMP dishing and erosion increase
Solution Approach 1:
The patent extracts dummy gates from the guard ring structure, eliminating the primary source of CMP dishing and erosion. By reducing the number of gate structures, the patent minimizes the harmful CMP effects while maintaining adequate source/drain formation control through alternative structural means.
Solution Approach 2:
The patent applies source/drain formation control measures selectively only where needed for device performance, rather than uniformly across the entire guard ring. This localized approach reduces the overall gate density and minimizes CMP dishing and erosion in non-critical areas.
3Manufacturing precision
If guard ring size is increased to accommodate dummy gates, then source/drain formation is constrained, but circuit area increases
Solution Approach 1:
The patent removes dummy gates from the guard ring, allowing the guard ring to be compacted to a smaller size. This extraction enables the same source/drain formation control to be achieved in a reduced area, thereby decreasing the overall circuit footprint.
Solution Approach 2:
Instead of using dummy gates to constrain source/drain formation, the patent inverts the approach by using the guard ring's source/drain regions and isolation structures themselves to provide the constraining function, eliminating the need for additional gate structures and reducing area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate density and the size of the well tap cell, minimizing CMP erosion and dishing effects while enhancing circuit area and device performance by providing reliable and consistent biasing for IC cells.
Implementation Method 1
uses a hard mask to define source/drain regions through etching
Implementation Method 2
epitaxial growth, which are constrained by a hard mask formed in the well tap cell
Data Source
AI summary
The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.