Non-imprinting Memory Cell with Master-Slave Data Exchange
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Solution Overview
Problem
Conventional memory technologies face issues with data imprinting, which allows sensitive information to be detected even after intended erasure, and existing erasure methods are not reliable or quick enough, posing security risks in applications like cryptographic systems and identity storage.
Innovation Solution
A memory cell design featuring a master and slave cell configuration with non-overlapping clock signals that constantly exchange and invert data states, preventing oxide charge accumulation and allowing for simultaneous and rapid erasure of data, thereby preventing imprinting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory cell designs are used, then data storage is achieved, but data imprinting occurs due to gate oxide charge accumulation from constant bias voltage
Solution Approach 1:
The patent applies periodic action by implementing a dual-cell architecture where data is continuously exchanged between master and slave cells at regular intervals. This periodic exchange prevents any single cell from being subjected to constant bias voltage, thereby preventing gate oxide charge accumulation and data imprinting while ensuring reliable data erasure when needed
2Productivity
If data is stored in one memory location for extended periods, then storage efficiency is improved, but imprinting occurs and security is compromised
Solution Approach 1:
The system maintains storage efficiency by keeping data readily accessible in the memory cells while applying periodic exchange operations. This ensures data is never static in one location long enough to cause imprinting, yet remains efficiently stored and retrievable, thus eliminating security risks without sacrificing productivity
Solution Approach 2:
The patent extracts the data from a single static storage location and distributes it between master and slave cells. By taking the data out of one cell and continuously exchanging it with another cell, the system prevents imprinting while maintaining storage efficiency
3Speed
If fast erasure methods are implemented, then security response time is improved, but reliability of complete erasure is reduced
Solution Approach 1:
The patent extracts data from both master and slave cells simultaneously through the exchange mechanism. When erasure is required, data is quickly removed from both cells at the same time, ensuring both fast erasure speed and complete erasure reliability since no residual data remains in either cell
4Object-generated harmful factors
If data is constantly moved to prevent imprinting, then imprinting is prevented, but power consumption increases and reliability issues arise
Solution Approach 1:
The system uses periodic exchange operations between master and slave cells rather than continuous data movement. This periodic action prevents imprinting by ensuring no cell remains under constant bias voltage, while consuming minimal power by being inactive between exchange cycles
Solution Approach 2:
The dual-cell architecture with automatic exchange mechanism serves itself to prevent imprinting without requiring external intervention or continuous power input. The system automatically exchanges data between cells based on clock signals, eliminating the need for constant host CPU intervention and reducing overall power consumption
Data Source
AI summary
A memory cell includes a master cell storing first true/complement data and a slave cell storing second true/complement data. A first circuit associated with the slave cell is operable responsive to a first clock signal to copy first true/complement data from the master cell into the slave cell with same state to be the second true/complement data. A second circuit associated with the master cell is operable response to a second clock signal, which is a non-overlapping complement of the first clock signal, to copy second true/complement data from the slave cell into the master cell with complementary state to be the first true/complement data. A read/write circuit includes circuitry for supporting true/complement data read and write operations with respect to the master cell in either same polarity or opposite polarity state. A state machine tracks polarity state of the first true/complement data so as to control whether a same polarity or opposite polarity state read operation is performed by the read/write circuit.