Non-inclusive Cache Access Control for Multi-Processor Coherency
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Solution Overview
Problem
Inclusive cache systems face challenges in maintaining data coherency across multiple processor copies, requiring updates or invalidations of all copies upon a write operation, which can lead to inefficiencies due to high activity levels in multi-processor systems.
Innovation Solution
Implementing a non-inclusive cache system with a shared cache agent that controls access based on activity levels, allowing or denying read and write requests to the shared cache memory, and allocating cache lines dynamically to manage coherency and reduce congestion by forwarding requests to system memory when activity thresholds are exceeded.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inclusive cache systems are used to maintain data coherency across multiple processor copies, then data coherency is improved, but system performance deteriorates due to the need to update or invalidate all other copies upon every write operation
Solution Approach 1:
The cache system is segmented into different types of cache lines: inclusive cache lines (stored in both local and shared caches) and non-inclusive cache lines (stored only in local cache). This segmentation allows the system to maintain coherency for critical data while avoiding unnecessary invalidations for non-critical data, thus resolving the contradiction between coherency and performance.
Solution Approach 2:
Different cache lines are assigned different coherency characteristics based on their usage patterns and importance. Non-inclusive cache lines are used for data where local copies are sufficient and invalidations are not needed, while inclusive cache lines are used for data requiring consistency across all processors. This local differentiation optimizes performance without sacrificing necessary coherency.
2Reliability
If shared cache memory is used to store coherent copies of data, then data availability is improved, but cache congestion increases when multiple processors access the same data simultaneously
Solution Approach 1:
The cache memory is segmented into shared cache regions and private cache regions. Shared cache regions store data that multiple processors need access to, while private cache regions store data specific to individual processors. This segmentation reduces congestion by directing processors to appropriate cache regions based on data ownership and access patterns.
Solution Approach 2:
A cache controller acts as an intermediary between processors and cache memory, managing access rights and routing decisions. The controller determines whether a processor can access shared cache memory or must use private cache, and mediates conflicts to prevent congestion while ensuring data availability.
3Adaptability or versatility
If cache lines are dynamically allocated to manage activity levels, then system adaptability is improved, but control complexity increases
Solution Approach 1:
The cache system implements feedback mechanisms where activity levels in shared cache memory are monitored and fed back to the cache controller. Based on this feedback, the controller dynamically adjusts cache allocation policies, routing decisions, and access permissions to adapt to current system conditions without requiring complex manual control.
Solution Approach 2:
The cache system performs self-adjustment through automatic policies that respond to activity patterns. When shared cache activity exceeds thresholds, the system automatically redirects traffic to private cache or system memory without external intervention, reducing control complexity while maintaining adaptability.
Data Source
AI summary
Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity.