Non-Inclusive Cache Storage With Dynamic Data Pointers

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Solution Overview

Problem

Existing multi-level cache systems face challenges in efficiently managing data storage with inclusive caches, which suffer from high space usage due to duplicate data and limited flexibility in handling different workload distributions across processor cores.

Innovation Solution

Implementing a non-inclusive cache architecture with a data pointer system that decouples tags from memory, allowing dynamic reassignment of data associations and supporting snoop filtering, while maintaining cache coherency and reducing space requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If inclusive cache architecture is used, then cache coherency is maintained, but space usage increases due to duplicate data storage

Engineering Contradiction:
Improvecache coherencyVSAvoidspace usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The cache is divided into two separate structures: a tag array that stores metadata and a data array that stores actual data. This segmentation allows the system to maintain coherency information in the tag array without duplicating full data copies in every cache level, thereby reducing space usage while preserving cache coherency through the tag structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A directory structure is introduced as an intermediary between cache tags and data storage. The directory contains data pointers that indirectly reference data locations, allowing the system to maintain coherency information without storing duplicate data copies. This intermediary structure enables space-efficient storage while maintaining the ability to track and manage cache coherency across multiple levels.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If non-inclusive cache architecture is used, then space requirements are reduced, but flexibility in handling workload distributions decreases

Engineering Contradiction:
Improvespace requirementsVSAvoidflexibility in handling workload distributions
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The cache tag array is designed to be dynamically reconfigurable, allowing tags to be reassigned to different data pointers based on workload patterns. This dynamic structure enables the cache to adapt to different workload distributions while maintaining the space-efficient non-inclusive architecture. The reassignable tags can be configured to prioritize frequently accessed data from different processor cores or memory regions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The cache system allows changes in tag-to-data pointer associations based on observed workload characteristics. By monitoring access patterns and dynamically adjusting which tags point to which data locations, the system can optimize performance for different workload distributions while maintaining reduced space requirements compared to inclusive caches.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If data pointers are decoupled from tags, then dynamic reassignment is enabled, but system complexity increases

Engineering Contradiction:
Improvedynamic reassignment capabilityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A directory structure serves as an intermediary layer between the tag array and data array, containing data pointers that mediate the relationship between tags and stored data. This intermediary simplifies the decoupling process by providing a structured mechanism for dynamic reassignment. Instead of directly managing complex tag-to-data mappings, the system uses the directory as a manageable intermediate structure that handles the complexity of pointer management and tag reassignment.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12430252B2Data storage in non-inclusive cache
Publication Date: 2025.09.30 SIFIVE INC
  • US12430252B2 patent drawing
  • US12430252B2 patent drawing
  • US12430252B2 patent drawing

AI summary

Systems and methods for data storage in a non-inclusive cache. An integrated circuit includes a cache that includes a databank with multiple entries configured to store respective cache lines and an array of cache tags. Each cache tag includes a data pointer that points to an entry in the databank. A method includes allocating the entry in the databank to the cache including the array of cache tags from amongst multiple caches in the integrated circuit by writing the data pointer to the cache tag in the array of cache tags.