Non-Inclusive Cache Tag-Data Decoupling for Snoop Filtering

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Solution Overview

Problem

Existing multi-level cache systems face challenges in managing data storage efficiently, particularly in non-inclusive caches, which suffer from reduced space usage and high overhead due to duplicate data, while inclusive caches compromise performance with snoop filtering.

Innovation Solution

Implementing a non-inclusive cache with a data pointer system that decouples tags from memory, allowing dynamic reassignment of data associations without copying, and supports snoop filtering through a Non-Inclusive Cache Inclusive Directory (NICID) architecture.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an inclusive cache architecture is used, then snoop filtering is supported, but space usage increases due to duplicate data storage

Engineering Contradiction:
Improvesnoop filtering supportVSAvoidspace usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The cache is divided into two separate structures: a tag array that stores address tags and a data array that stores actual data. The tag array is further segmented into valid bits and tag data, allowing independent management of metadata and payload. This segmentation enables the cache to track data presence without duplicating full data copies, reducing space overhead while maintaining snoop filtering capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A directory structure acts as an intermediary between the inclusive cache requirements and the non-inclusive storage implementation. The directory maintains information about data presence and validity, enabling snoop filtering operations without requiring actual data duplication. This intermediary layer decouples the filtering logic from data storage, allowing space-efficient implementation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If a non-inclusive cache is used, then space usage is reduced, but overhead increases due to data pointer management

Engineering Contradiction:
Improvespace usageVSAvoidoverhead
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The data pointer management is merged with the existing tag structure. Instead of separate pointer arrays, the valid bits and tag data in the tag array serve dual purposes: traditional cache tagging and data location tracking. This merging eliminates redundant storage structures and reduces overhead while maintaining non-inclusive cache benefits.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The tag array structure is designed to perform multiple functions simultaneously: address matching, validity tracking, and data location indexing. By making the tag structure universal, the patent eliminates the need for separate data pointer management structures, reducing overall system overhead while enabling non-inclusive cache operation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If data is decoupled from tags using data pointers, then dynamic reassignment is enabled, but access complexity increases

Engineering Contradiction:
Improvedynamic reassignmentVSAvoidaccess complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The cache implementation uses dynamically allocatable arrays for both tag and data storage, allowing the cache to adapt its structure based on workload requirements. The tag array and data array can be independently sized and reconfigured, enabling dynamic reassignment of data associations without fixed structural constraints. This dynamic approach maintains flexibility while keeping access paths straightforward through consistent indexing mechanisms.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20260017199A1Data storage in non-inclusive cache
Publication Date: 2026.01.15 SIFIVE INC
  • US20260017199A1 patent drawing
  • US20260017199A1 patent drawing
  • US20260017199A1 patent drawing

AI summary

Systems and methods are disclosed for data storage in a non-inclusive cache. For example, an integrated circuit may include a cache that includes a databank with multiple entries configured to store respective cache lines; and an array of cache tags, wherein each cache tag includes a data pointer that points to an entry in the databank. For example, methods may include allocating the entry in the databank to the cache including the array of cache tags from amongst multiple caches in the integrated circuit by writing the data pointer to the cache tag in the array of cache tags.