Non-Interleaved DAG Software Execution with Multicore Fork-Join Coordination
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Solution Overview
Problem
Existing algorithms for on-board systems that utilize multi-core microprocessors face challenges in maintaining real-time behavior and data coherence while leveraging the power of multiple cores, as they were originally designed for single-core execution.
Innovation Solution
A method for implementing a software module defined by a non-interleaved directed acyclic graph, utilizing fork and join functions to allocate executable units across multiple cores, ensuring precise sequence execution and real-time performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If algorithms originally designed for single-core execution are re-used on multi-core microprocessors, then the power of multiple cores can be utilized, but real-time behavior and data coherence may not be preserved
Solution Approach 1:
The software module is segmented into executable units represented as nodes in a directed acyclic graph, where each node can be independently allocated to a specific core. This segmentation allows the algorithm to be divided into parallel-executable components while maintaining the original execution logic and real-time behavior through the graph's structured relationships.
Solution Approach 2:
The patent transitions from sequential single-core execution to parallel multi-core execution by introducing a spatial dimension (core allocation) to the execution model. The directed acyclic graph enables executable units to be distributed across multiple cores simultaneously, achieving parallelism while preserving real-time constraints through the graph's topological ordering.
2Speed
If executable units are distributed across multiple cores in parallel, then system response time can be improved, but maintaining execution sequence and data coherence becomes complex
Solution Approach 1:
The execution sequence and core allocations are predetermined during the graph construction phase. Each node in the directed acyclic graph is pre-assigned to a specific core and the execution order is established through the graph's topological structure, eliminating the need for complex runtime coordination and synchronization mechanisms.
Solution Approach 2:
The directed acyclic graph serves as an intermediary structure that mediates between the executable units and the multi-core processor. The graph's nodes and edges encode the execution sequence and dependencies, allowing the system to achieve parallel execution while maintaining coherence through the graph's structural constraints rather than complex software synchronization.
3Productivity
If fork and join functions are used to parallelize execution, then multiple cores can execute simultaneously, but waiting times at join points may increase
Solution Approach 1:
The patent dynamically allocates executable units to cores based on the directed acyclic graph structure and system state, rather than using static fork-join patterns. This dynamic allocation allows the system to optimize execution paths and minimize waiting times by adaptively distributing work across available cores, avoiding the inherent synchronization delays of traditional fork-join approaches.
Data Source
AI summary
An elementary method for implementing a software module defined by an elementary directed acyclic graph, including the following steps: copying the code of the initial sequence, adding a fork function at the end of the initial sequence, copying the code of a parallel sequence, adding a join flag function at the end of said parallel sequence, copying the code of the other parallel sequence, adding a join wait function at the end of the other parallel sequence.