Non-interleaved Scan Architecture for IC Test Time Reduction
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Solution Overview
Problem
In low power integrated circuit (IC) designs, the output buffers are restricted to lower speed operation to conserve power, limiting the total test time due to the scan speed determined by these buffers in conventional scan architectures.
Innovation Solution
Adapting conventional scan architectures to a high-speed scan architecture using a non-interleaved scan procedure and asymmetric compressor-decompressor (CoDec) architecture, where all available scan pins act as inputs during the scan load mode and operate as outputs during the scan unload mode, leveraging the higher frequency capability of input ports to reduce test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If output buffers operate at lower speed to save power, then power consumption is reduced, but test time increases due to limited scan speed
Solution Approach 1:
The scan operation is segmented into two distinct phases: scan load mode for input operations and scan unload mode for output operations. This segmentation allows each phase to use optimized buffering strategies appropriate to its specific requirements, enabling high-speed input loading while maintaining low-power output unloading.
Solution Approach 2:
The buffer operation mode is made dynamic by switching between input mode and output mode based on the current scan phase. During scan load mode, input buffers operate at high speed while output buffers remain in low-power state. During scan unload mode, the roles reverse. This dynamic switching resolves the contradiction by allowing high performance when needed and low power consumption when possible.
2Device complexity
If scan input and scan output share the same I/O pins, then pin count is reduced, but scan speed is limited by the slower output buffers
Solution Approach 1:
The shared I/O pins undergo periodic action by alternating between input mode and output mode in distinct time phases. During scan load mode, pins operate as high-speed inputs; during scan unload mode, pins operate as output buffers. This periodic switching allows the same physical pins to achieve both high-speed input capability and output functionality, resolving the speed limitation imposed by sharing pins.
Solution Approach 2:
The functional mode of the I/O pins is made dynamic, switching between input and output configurations based on the current scan phase. This dynamic reconfiguration allows the pins to operate at high speed during input operations while maintaining compatibility with lower-speed output requirements during unload operations, effectively resolving the speed-pin count contradiction.
3Loss of time
If overlapped scan operation is used, then test time is reduced through parallel processing, but scan output speed becomes the bottleneck
Solution Approach 1:
The overlapped scan operation is segmented into distinct load and unload phases with different performance characteristics. During scan load mode, the system achieves high throughput by loading test patterns at maximum input buffer speed. During scan unload mode, the system operates at the slower output buffer speed. This segmentation allows the overall test time to be dominated by the faster input operations, improving productivity while maintaining the benefits of overlapped operation.
Solution Approach 2:
The operational parameters of the scan buffers are changed dynamically between phases: during scan load mode, input buffers operate at high frequency with maximum data rate, while during scan unload mode, output buffers operate at their maximum (lower) frequency. This parameter change allows the system to achieve higher overall throughput by spending more time in the high-speed input phase, resolving the contradiction between reduced test time and scan throughput.
Data Source
AI summary
A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.