Non-Intrusive HLS Profiling for Cycle-Accurate Bottleneck Tracing
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Solution Overview
Problem
Existing High-Level Synthesis (HLS) tools for Field Programmable Gate Arrays (FPGAs) lack non-intrusive performance profiling methods, leading to difficulties in identifying performance bottlenecks and optimizing hardware designs due to the lack of direct correspondence between source code and performance information, and existing profiling tools introduce performance overheads or require intrusive circuitry.
Innovation Solution
A method and system for non-intrusive profiling that synthesizes HLS-based applications using an HLS compiler, co-simulates HDL files, and employs an HLS profiler to parse various reports and files to associate HDL signals with source code variables, generating a cycle-by-cycle performance profile table using associative rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing profiling tools are used to collect performance data, then performance profiling information can be obtained, but performance overheads are introduced
Solution Approach 1:
The patent introduces an intermediate database layer that stores the mapping relationship between HDL signals and source code variables. The profiler queries this database to obtain profiling information without directly instrumenting the application code, thus avoiding performance overhead while maintaining measurement precision.
Solution Approach 2:
Instead of modifying the original application code to add profiling instructions, the patent creates a copy of the variable mapping information in a database. This copy contains all the necessary correspondence data between HDL signals and source code, allowing profiling without touching the performance-critical application code.
2Measurement precision
If intrusive circuitry is added to collect profile data, then detailed performance information can be obtained, but device complexity increases
Solution Approach 1:
The patent replaces the mechanical approach of adding physical profiling circuitry to the FPGA with a software-based solution. The HLS compiler automatically generates HDL code that includes variable declarations and mappings, which are then stored in a database. This software-generated information structure substitutes for hardware circuitry, reducing device complexity while maintaining profiling capability.
3Measurement precision
If line-by-line profiling is implemented, then detailed source code performance information can be obtained, but the profiling becomes intrusive
Solution Approach 1:
The patent performs preliminary action by having the HLS compiler automatically generate the variable mapping information during the synthesis phase, before profiling is needed. This mapping information is stored in a database, so when profiling occurs, the system simply queries pre-prepared data rather than collecting it intrusively during execution, achieving detailed line-by-line information without intrusiveness.
4Measurement precision
If HLS tools provide overall latency information, then performance metrics can be obtained, but cycle-accurate source code level information is not available
Solution Approach 1:
The patent segments the overall latency information into fine-grained, cycle-accurate measurements at the source code variable level. By maintaining a database of HDL signal to source code variable mappings, the profiler can attribute timing information from the HDL simulation to specific lines of source code, providing detailed cycle-accurate information that was previously lost in aggregate latency measurements.
Data Source
AI summary
State of the art techniques provide dedicated High-Level Synthesis (HLS) performance estimator tools that can give insights on performance bottlenecks, stall rate, stall cause etc., in HLS designs. These estimators often limit themselves to simple loop topologies and limited pragma use which makes them unreliable for large designs with complex datapaths. Embodiments herein provide a method and system for non-intrusive profiling for high-level synthesis HLS based applications. The method provides a cycle-accurate, fine-grained performance profiling framework that is non-intrusive and provides an end-to-end profile of the design. Such profiling tool can help the designer/DSE tool to quickly identify the performance bottlenecks and have a guided approach towards tuning it.