Non-Inverting TDC Delay Chain for PVT-Robust Phase Detection
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Solution Overview
Problem
Current time-to-digital converters (TDCs) in digital radio frequency processors face design and layout issues due to inverting polarity across stages, leading to uneven transition times and unbalanced metastability, which affect resolution and robustness against process, voltage, and temperature variations.
Innovation Solution
A TDC system employing non-inverting buffers and transmission gates to delay clock signals, providing buffer-delayed and gate-delayed clock signals, along with a non-linearity corrector to calibrate and correct for delay mismatches, ensuring robustness and high resolution without polarity inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If inverter gates are used as delay elements to achieve high timing resolution, then timing resolution is improved, but design and layout complexity increases due to polarity inversion issues
Solution Approach 1:
The patent inverts the conventional approach by using non-inverting buffers instead of inverting gates as delay elements. This eliminates the polarity inversion problems that complicate design and layout while maintaining the short delay characteristics needed for high timing resolution. The non-inverting buffers provide the necessary delay without the associated metastability and matching issues.
Solution Approach 2:
The patent changes the fundamental parameter of the delay element from inverting to non-inverting operation. By modifying the operational mode of the delay element, the patent achieves high timing resolution without the design and layout complexities associated with polarity inversion, effectively resolving the contradiction between measurement precision and device complexity.
2Measurement precision
If inverter gates are used as delay elements, then timing resolution is improved, but reliability decreases due to uneven transition times and unbalanced metastability across PVT variations
Solution Approach 1:
The patent resolves the reliability issue by inverting the conventional approach - using non-inverting buffers instead of inverting gates. This eliminates the uneven transition times and unbalanced metastability that occur with inverter-based designs under PVT variations, while preserving the short delay needed for high timing resolution.
Solution Approach 2:
The patent achieves homogeneous transition characteristics across all delay stages by using identical non-inverting buffer structures. This homogeneity ensures that rising and falling edges experience consistent delay and metastability behavior across process, voltage, and temperature variations, thereby improving reliability while maintaining high timing resolution.
3Device complexity
If non-inverting buffers and transmission gates are used instead of inverter gates, then design complexity is reduced, but delay precision may be affected
Solution Approach 1:
The patent segments each delay stage into two distinct components: a non-inverting buffer providing the main delay and transmission gates providing fine-tuned delay adjustment. This segmentation allows independent optimization of each component - the buffer for robustness and the transmission gates for precision - thereby achieving both reduced design complexity and maintained delay precision.
Solution Approach 2:
The transmission gates act as intermediary elements between the non-inverting buffers, providing fine-tuned delay adjustment. This intermediary mechanism allows precise control of delay characteristics without requiring complex inverter-based designs, thereby maintaining delay precision while simplifying the overall architecture.
Data Source
AI summary
A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.