Seamless Non-Linear to Linear Voltage Regulation Control
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Solution Overview
Problem
Modern processors and system-on-chips face challenges with increasing di/dt rates, leading to voltage droop and chatter on output supply nodes, which result in indeterministic Vmin and require larger guardbands, complicating high-volume manufacturing and validation.
Innovation Solution
A digital control scheme is implemented for a PID Type-III controller, transitioning seamlessly from non-linear to linear regulation modes, using a finite state machine to manage duty cycles and eliminate chatter, ensuring deterministic droop and reducing the need for VID boost features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-linear clamp (NLC) is used to minimize voltage droop impact, then voltage droop is reduced, but output voltage chatter occurs due to bandwidth discrepancy between non-linear and linear control loops
Solution Approach 1:
The patent implements dynamic control loop bandwidth adjustment by modifying the linear controller bandwidth to match the non-linear controller bandwidth during transient conditions. This is achieved through dynamic modification of the proportional-integral-derivative (PID) controller parameters, allowing the system to transition from fixed bandwidth to adaptive bandwidth control, thereby eliminating chatter while maintaining voltage droop mitigation.
Solution Approach 2:
The patent changes the bandwidth parameter of the linear control loop dynamically based on operating conditions. By adjusting the PID controller parameters (proportional gain, integral gain, derivative gain) in response to load transients, the system optimizes the bandwidth match between control loops, resolving the chatter issue without sacrificing voltage regulation performance.
2Stability of the object's composition
If traditional linear control is used to ensure output voltage settles, then voltage stability is achieved, but it cannot cope with increasing di/dt rates causing voltage droop
Solution Approach 1:
The patent merges the advantages of both non-linear and linear control by integrating them into a unified control system. The non-linear clamp provides fast response to voltage droop, while the modified linear controller with adaptive bandwidth ensures smooth settling. The combination leverages the high bandwidth of non-linear control and the stability of linear control, achieving both voltage droop mitigation and chatter-free operation.
Solution Approach 2:
The patent implements preliminary action by proactively adjusting the linear controller bandwidth before voltage droop occurs or during early transient stages. The predictive current mode control and adaptive bandwidth adjustment prepare the linear controller to respond effectively, preventing voltage droop before it significantly impacts the output while ensuring smooth transition to steady-state operation.
3Speed
If non-linear controller operates at high bandwidth to respond quickly, then fast voltage recovery is achieved, but it causes chatter requiring multiple NLC actions
Solution Approach 1:
The patent implements feedback mechanisms where the output of the non-linear controller and the state of the linear controller are continuously monitored. This feedback enables the system to detect when voltage recovery is complete and when to transition control to the linear controller, preventing chatter and reducing the need for multiple NLC actions. The feedback loop adjusts control parameters based on real-time voltage and current conditions.
Data Source
AI summary
A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.