Multi-Stage Non-Linear PUF Circuit for IoT Authentication

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Solution Overview

Problem

IoT devices face challenges in secure authentication due to the vulnerability of traditional cryptographic protocols to probing and side-channel attacks, and current Physically Unclonable Function (PUF) circuits are susceptible to machine learning attacks due to linear response bits.

Innovation Solution

A multi-stage non-linearly cascaded all-digital PUF circuit is developed, utilizing re-configurable cross-coupled inverters and non-linear mapping functions like AES S-boxes to create a large challenge-response space, providing machine learning resistance while maintaining a low area and energy footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional cryptographic protocols with stored keys are used, then authentication security is provided, but the system becomes vulnerable to probing and side-channel attacks and requires more area and energy

Engineering Contradiction:

Improveauthentication securityVSAvoidvulnerability to probing and side-channel attacks

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the secret key storage function from the authentication system and replaces it with a PUF circuit that generates keys on-demand from physical characteristics, eliminating the vulnerability of stored keys to probing and side-channel attacks

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The PUF circuit generates cryptographic keys autonomously from its own physical characteristics without requiring external key storage or management, making the system self-sufficient and resistant to key extraction attacks

Inventive Principle:

Principle #25Self-service

2Use of energy by moving object

If current PUF circuits with linear response bits are used, then area and energy constraints are satisfied, but the system becomes vulnerable to machine learning attacks

Engineering Contradiction:

Improveenergy consumptionVSAvoidresistance to machine learning attacks

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent transforms the PUF response from linear to non-linear by applying non-linear mapping functions, adding a new dimension of complexity that prevents machine learning attacks while maintaining the low area and energy characteristics of digital PUF circuits

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the mathematical relationship between challenge and response from linear to non-linear through the application of non-linear mapping functions, fundamentally altering the system's resistance properties against machine learning attacks

Inventive Principle:

Principle #35Parameter changes

3Reliability

If non-linear mapping functions are applied in multi-stage cascaded PUF circuits, then machine learning resistance is increased, but the device complexity increases

Engineering Contradiction:

Improvemachine learning resistanceVSAvoidcircuit structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the PUF circuit into multiple stages, each applying a non-linear mapping function to intermediate results, which distributes the complexity across manageable segments while achieving cumulative security enhancement against machine learning attacks

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10530588B2Multi-stage non-linearly cascaded physically unclonable function circuit

Publication Date: 2020.01.07 INTEL CORP

AI summary

An apparatus is provided which comprises: a first stage of physically unclonable function (PUF) circuits to receive an n-bit challenge, wherein the first stage of PUF circuits comprise a subset of ‘n’ PUF cells each of which is to generate an output bit; and a first stage of cipher blocks to receive the output bits from the subset of ‘n’ PUF cells, wherein the first stage of cipher blocks is to generate a plurality of bits.