Non-Orthogonal Rectangular Cell Layout for Semiconductor Routing
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor devices lead to challenges such as high yield loss, reduced reliability of electrical interconnections, and low testing coverage, necessitating improvements in device robustness and manufacturing efficiency.
Innovation Solution
The introduction of non-orthogonal cell structures, such as parallelogram and crisscross layouts, which allow for increased conductive line routing without expanding the cell area, enhancing electrical connectivity and reducing design rule violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional rectangular cell structures are used, then manufacturing process is simple, but routing efficiency is limited and design rule violations occur
Solution Approach 1:
The patent applies asymmetry by introducing non-orthogonal cell structures where at least one cell side is inclined relative to the substrate, breaking the conventional symmetric rectangular layout. This asymmetric design enables improved routing efficiency and reduces design rule violations while maintaining manufacturing feasibility through controlled inclination angles
2Productivity
If cell area is increased to accommodate more conductive lines, then routing capacity improves, but area usage efficiency decreases
Solution Approach 1:
The patent utilizes dimensionality change by introducing inclined cell sides that create non-orthogonal orientations. This allows conductive lines to be routed more efficiently within the same cell area by exploiting the additional spatial dimension created by the inclination, thereby increasing routing capacity without expanding the cell footprint
3Productivity
If miniaturization is pursued to increase functional density, then device integration improves, but manufacturing complexity and yield loss increase
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of the cell structure, specifically the inclination angle of cell sides relative to the substrate. This parameter modification enables improved routing efficiency and reduced design rule violations at miniaturized scales, thereby supporting higher functional density while managing manufacturing complexity
Data Source
AI summary
A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.