Non-orthogonal gate electrode interconnection layout
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Solution Overview
Problem
The challenge in semiconductor integrated circuit (IC) manufacturing is the efficient formation of interconnections between elements, which occupy valuable layout area and become complex as geometry sizes decrease, necessitating innovative patterning methods to reduce layout area and enhance processing efficiency.
Innovation Solution
A method for fabricating semiconductor devices that involves forming non-orthogonal cuts in gate structure elements, allowing for slanted interconnections between adjacent gate structures, which reduces layout area and simplifies the patterning process by using a combination of photolithography and etching techniques to create inclined cuts and spacer formations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If orthogonal cuts are used to form interconnections between gate structures, then the patterning process is simple and straightforward, but the layout area occupied by interconnections is large and valuable chip area is wasted
Solution Approach 1:
The patent applies asymmetry by transitioning from traditional orthogonal (90-degree) cuts to non-orthogonal (e.g., 45-degree) cuts in gate structure patterning. This asymmetric approach allows interconnection elements to be positioned more efficiently, reducing the layout area occupied by interconnections while maintaining electrical connectivity between gate structures.
2Productivity
If geometry size is decreased to increase functional density, then production efficiency increases and costs decrease, but the complexity of processing and manufacturing increases
Solution Approach 1:
The patent segments the gate structures into multiple sections using non-orthogonal cuts, allowing each segment to be independently positioned and connected. This segmentation enables efficient packing of interconnections at smaller geometries while maintaining manageable processing complexity through systematic patterning approaches.
Solution Approach 2:
The patent introduces non-orthogonal cutting angles as an additional dimensional parameter beyond traditional orthogonal patterning. This dimensional change enables more flexible interconnection routing and reduces layout area requirements, allowing higher functional density without proportionally increasing processing complexity.
3Reliability
If more interconnection elements are added to connect gate structures, then electrical connectivity is improved, but the layout area increases and valuable chip space is consumed
Solution Approach 1:
By using non-orthogonal cut angles, the patent enables interconnection elements to be arranged more compactly and efficiently. This asymmetric positioning reduces the total layout area required for interconnections while maintaining adequate electrical connectivity between gate structures, effectively decoupling connectivity requirements from area consumption.
Data Source
AI summary
The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.