Non-Overlapping Clock Generator for Low-Power Pipelined ADCs
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Solution Overview
Problem
Existing analog-to-digital converter (ADC) technologies face challenges in generating non-overlapping clock signals efficiently, particularly in switched capacitor circuits, which can lead to charge transfer errors and require innovative clock generation circuits that maintain high sample rates while minimizing power consumption.
Innovation Solution
A non-overlapping clock generator circuit architecture that supplies clock signals with specific timing relationships to pipelined ADC stages, allowing middle stages to operate at a reduced frequency, thereby reducing power consumption while maintaining the overall sample frequency through parallel input sampling circuitry and shared operational amplifiers in switched capacitor circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If clock generation circuits generate non-overlapping clock signals for switched capacitor circuits, then charge transfer errors are reduced, but device complexity increases
Solution Approach 1:
The patent combines multiple clock signal generation functions into a single integrated clock generation circuit that produces non-overlapping clock signals for multiple switched capacitor circuits simultaneously. This merging approach reduces the overall number of separate clock generation circuits needed, thereby reducing device complexity while maintaining conversion accuracy.
Solution Approach 2:
The clock generation circuit uses periodic non-overlapping clock signals with carefully controlled phases to drive the switched capacitor circuits. By designing the clock signals to have specific periodic relationships and non-overlapping phases, the circuit achieves precise charge transfer timing without requiring complex control logic, thus resolving the contradiction between accuracy and complexity.
2Use of energy by moving object
If middle stages operate at reduced frequency to lower power consumption, then power usage decreases, but sample rate capability is reduced
Solution Approach 1:
The patent divides the ADC into multiple stages with different operating frequencies. The first stage operates at the full input sample rate, while subsequent middle stages operate at reduced frequencies. This segmentation allows the system to maintain high sample rate capability at the input while reducing power consumption in the middle stages, as they process data at lower rates.
Solution Approach 2:
The patent implements dynamic frequency scaling where different stages of the ADC operate at different clock frequencies optimized for their specific functions. The clock generation circuit dynamically provides appropriate frequency ratios between stages, allowing middle stages to operate efficiently at lower frequencies while the overall system maintains high sample rate capability through the parallel architecture.
3Productivity
If parallel input sampling circuitry is used to maintain high sample rates, then productivity increases, but device complexity increases
Solution Approach 1:
The patent designs the middle stages with parallel input sampling circuitry that can handle multiple input channels simultaneously. Each middle stage is designed to be multi-functional, processing samples from different sources in parallel while sharing common resources such as operational amplifiers and clock generation circuits. This universality approach maintains high sample rate capability without proportionally increasing overall device complexity.
Data Source
AI summary
A non-overlapping clock generator circuit supplies clock signals to a stage of a pipelined ADC, which includes parallel switched capacitor circuitry. The non-overlapping clock generator circuit includes: a first trigger generation circuit that generates first and second trigger signals; a second trigger generation circuit that generates third and fourth trigger signals; a first clock generation branch that receives the first, second and fourth trigger signals and generates first sampling cycle and delayed sampling cycle clock signals; a second clock generation branch that receives the first, second and third trigger signals and generates second sampling cycle and delayed sampling cycle clock signals; a third clock generation branch that receives the second trigger signal and generates first gain cycle and delayed gain cycle clock signals; and a fourth clock generation branch that receives the first trigger signal and generates second gain cycle and delayed gain cycle clock signals.