Non-Overlapping Frequency Doubler for Low-Power Compact Circuits

Solution Overview

Problem

Conventional frequency doublers, particularly those using phase lock loop (PLL) circuits, have large area requirements, complex structures, and high power consumption, making them unsuitable for power-consumption-sensitive devices and requiring a more compact and efficient solution.

Innovation Solution

A frequency doubler comprising a non-overlapping signal generation circuit and a combination circuit that generates non-overlapping signals with controlled duty cycles, allowing for precise frequency doubling with lower power consumption and complexity, and is adaptable for integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a PLL circuit is used for frequency doubling, then frequency doubling function is achieved, but the area becomes very large and structure becomes complicated

Engineering Contradiction:

Improvefrequency doubling functionVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The frequency doubler is segmented into three functional modules: a first signal generation circuit that receives the input signal and generates two non-overlapping signals with complementary duty cycles, a second signal generation circuit that generates clock signals based on the non-overlapping signals, and a combination circuit that combines the clock signals to produce the frequency-doubled output. This modular segmentation reduces the overall circuit area and simplifies the structure compared to a conventional PLL circuit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention extracts and eliminates the PLL circuit from the frequency doubler design. By removing the PLL component entirely and replacing it with a direct non-overlapping signal generation approach, the circuit area is significantly reduced while maintaining the frequency doubling function. The patent explicitly states that PLL circuits are eliminated in favor of this more compact architecture.

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If a PLL circuit is used for frequency doubling, then frequency doubling function is achieved, but power consumption increases

Engineering Contradiction:

Improvefrequency doubling functionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The frequency doubler is segmented into three functional modules: a first signal generation circuit that receives the input signal and generates two non-overlapping signals with complementary duty cycles, a second signal generation circuit that generates clock signals based on the non-overlapping signals, and a combination circuit that combines the clock signals to produce the frequency-doubled output. This modular segmentation reduces the overall circuit area and simplifies the structure compared to a conventional PLL circuit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention extracts and eliminates the PLL circuit from the frequency doubler design. By removing the PLL component entirely and replacing it with a direct non-overlapping signal generation approach, the circuit area is significantly reduced while maintaining the frequency doubling function. The patent explicitly states that PLL circuits are eliminated in favor of this more compact architecture.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If conventional frequency doubler design is used, then frequency doubling is achieved, but duty cycle precision is poor

Engineering Contradiction:

Improvefrequency doubling functionVSAvoidduty cycle precision

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The first signal generation circuit is designed to generate two non-overlapping signals with complementary duty cycles (one signal has duty cycle D, the other has duty cycle 1-D). This local quality control at the signal generation stage ensures that the subsequent clock signals and final output maintain precise duty cycle characteristics. The combination circuit preserves these duty cycle properties, achieving precise frequency doubling with controlled duty cycle.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8269530B2Frequency doubler, a device including the same and a method for frequency doubling

Publication Date: 2012.09.18 BEKEN CORP

AI summary

A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.