Non-overlapping Gate Electrode Reduces Parasitic Capacitance
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Solution Overview
Problem
In display devices, the increasing demand for higher resolution and faster frame rates leads to the need for miniaturized transistors, but existing transistors with overlapping wiring cause parasitic capacitance, resulting in RC delay and reduced display performance.
Innovation Solution
A semiconductor device with a top-gate transistor structure is designed, where the gate electrode does not overlap with the source and drain electrodes, and the end parts of these electrodes are arranged to minimize parasitic capacitance by matching or being inside the oxide semiconductor layer's surface, reducing the RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate electrode overlaps with the source and drain electrodes to simplify the transistor structure, then the device complexity is reduced, but parasitic capacitance increases causing RC delay
Solution Approach 1:
The patent transitions from a planar overlapping gate structure to a three-dimensional configuration where the gate electrode is positioned above the oxide semiconductor layer without overlapping the source and drain electrodes. This spatial rearrangement in the vertical dimension eliminates parasitic capacitance between the gate and source/drain electrodes while maintaining effective gate control over the channel region.
2Area of moving object
If the transistor size is reduced to increase resolution, then the area is decreased, but parasitic capacitance effects become more significant increasing RC delay
Solution Approach 1:
By positioning the gate electrode above the oxide semiconductor layer in a non-overlapping configuration, the patent eliminates parasitic capacitance pathways that would otherwise scale adversely with device miniaturization. This three-dimensional arrangement allows transistors to be scaled down in area without the RC delay penalties that typically accompany reduced dimensions.
3Speed
If the frame rate is increased to improve display performance, then the speed is improved, but the RC delay becomes more critical limiting further speed increases
Solution Approach 1:
The patent converts the potential harm of parasitic capacitance into a benefit by adopting a gate structure that inherently minimizes this effect. The non-overlapping gate electrode configuration above the oxide semiconductor layer transforms what would be a limiting factor for high-speed operation into an enabler for achieving higher frame rates by suppressing RC delay.
Data Source
AI summary
A semiconductor device includes an oxide semiconductor layer above an insulating surface, a source electrode in contact with a side surface of the oxide semiconductor layer, a drain electrode in contact with a side surface of the oxide semiconductor layer, a gate insulating film above the oxide semiconductor layer, the source electrode, and the drain electrode, and, a gate electrode overlapping with the oxide semiconductor layer interposed by the gate insulating film. The gate electrode is arranged above and outside of the source electrode and the drain electrode.