Non-Overlapping Triangle Path Rendering for Graphics Efficiency
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Solution Overview
Problem
Current 2D-graphics rendering methods, particularly when using transparency, face computational inefficiencies due to the need for costly tessellation and overlapping polygon analysis, which can result in visual artifacts and high CPU load, especially in resource-constrained devices like handheld devices.
Innovation Solution
A method that represents a path's stroke using a plurality of non-overlapping triangles, where each straight line is represented by two triangles and joins are handled by creating a mask based on these triangles, reducing computational complexity and data transfer between CPU and GPU, allowing for efficient rendering by moving tessellation to the rasterizer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complete tessellation process is performed to break down the outline into polygons and remove overlapping polygons, then visual artifacts from overlapping transparent paths are eliminated, but the computational complexity increases to O(n log(n)) and processing time is significantly increased
Solution Approach 1:
The patent extracts and removes only the overlapping portions of the outline that cause visual artifacts, rather than performing a complete tessellation and removal of all overlapping polygons. This selective extraction approach maintains visual accuracy while significantly reducing computational complexity from O(n log(n)) to O(n).
Solution Approach 2:
The patent applies partial action by performing only the necessary tessellation steps to identify and remove overlapping regions, rather than completing the full tessellation process. This partial approach achieves the required visual accuracy without the full computational cost of complete tessellation and polygon analysis.
2Reliability
If a mask is generated through complete tessellation to represent the path stroke, then overlapping areas are correctly handled, but the CPU load and memory bandwidth consumption increase significantly
Solution Approach 1:
The patent extracts only the essential mask information needed to represent the path stroke without performing complete tessellation. By removing unnecessary computational steps and keeping only the critical mask generation operations, the patent reduces CPU load while maintaining rendering accuracy.
3Quantity of substance
If polygons representing the mask are fed to the rasterizer instead of the entire mask image, then bus load between CPU and hardware rasterizer is reduced, but the CPU load for generating the polygons remains high due to complete tessellation
Solution Approach 1:
The patent extracts only the necessary polygon data from the path outline without performing complete tessellation. By removing redundant computational steps and extracting only the essential geometric information needed for mask representation, the patent reduces both CPU load and data transfer requirements to the rasterizer.
Solution Approach 2:
The patent applies partial action by performing only the minimal tessellation needed to generate the polygon representation of the mask, rather than completing the full tessellation process. This partial approach achieves sufficient accuracy for mask generation while significantly reducing CPU efficiency requirements.
Data Source
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AI summary
A method of rendering a path, comprising at least two straight lines and at least one join connecting two of the at least two straight lines, is disclosed. The method is suitable for use in a device having graphics processing capabilities. The method comprises determining a mask associated with a stroke of the path and representing the mask by a plurality of triangles, wherein each of the at least two straight lines are represented by two triangles and the triangles representing two straight lines connected by one join are non-overlapping. The method also comprises creating the mask based on the plurality of triangles and rendering the path by filling the mask. Corresponding computer program product, arrangement and electronic device are also disclosed.