Non-Planar Chip Assembly Using Slots and Stressed Films
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Solution Overview
Problem
Traditional planar technologies in the integrated circuit industry limit the geometry of interactions and interconnections among devices and with external systems, making it difficult to achieve non-planar geometries that could simplify these interactions.
Innovation Solution
The method involves creating slots on thin semiconductor chips and depositing stressed films to allow for deformation, which can be bonded to constraining elements to form curved surfaces, enabling larger deformations and non-planar geometries suitable for applications like brain-machine interfaces and 3D signal processing units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If planar technology is used to reduce feature size limit of photolithography, then manufacturing precision is improved, but device geometry complexity is reduced limiting interactions among devices
Solution Approach 1:
The patent applies curvature to semiconductor chips by creating non-planar three-dimensional structures. Multiple chips are bonded together in stacked configurations with lateral offsets, forming curved or spherical arrangements that enable complex geometric interactions while maintaining planar manufacturing processes for each individual chip layer.
Solution Approach 2:
The invention transitions from two-dimensional planar chip arrangements to three-dimensional stacked configurations. By bonding multiple chips vertically with lateral offsets, the system achieves complex spatial geometries and interaction patterns that are impossible with planar technology alone, while each chip layer retains planar manufacturing benefits.
2Device complexity
If non-planar geometries are created to minimize complexity of interactions among devices, then device complexity is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the overall non-planar device into multiple individual planar chip layers. Each chip is manufactured separately using standard planar photolithography processes, then bonded together in stacked configurations. This segmentation allows complex three-dimensional geometries to be achieved through assembly of simple planar components, maintaining manufacturing ease while achieving interaction complexity reduction.
Solution Approach 2:
The invention implements nested stacking where multiple chip layers are bonded vertically with lateral offsets, creating a nested three-dimensional structure. Each chip layer is contained within the overall device structure, with chips bonded to adjacent chips in the stack. This nesting approach enables complex spatial arrangements while using standard planar manufacturing for each chip layer.
3Adaptability or versatility
If chips are bonded to constraining elements to allow larger deformation, then adaptability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent creates slots or openings in the chip structures before bonding to constraining elements. These pre-formed slots accommodate the bonding process and allow the chips to deform to desired curved configurations. By preparing the chip geometry in advance with appropriate slots, the bonding operation can achieve the required precision more easily, as the slots provide tolerance for alignment and deformation during the bonding process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of non-planar integrated circuit devices that can be curved to desired shapes, reducing complexity in interactions and enabling new computational architectures and interfaces with biological systems, such as retinal prostheses, by allowing for closer proximity of micro electrodes to neuron cells.
Implementation Method 1
stressed films may be deposited on either side (or both sides) of a thin semiconductor substrate of a thin chip for small deformations of the chip
Implementation Method 2
The slots may be created as longitudinal openings in the chips to reduce bending stresses to increase allowable degrees of deformation of the chips
Implementation Method 3
Two or more slotted pieces of the chips may be bonded to have mutual or multiple constraints to hold curved pieces in place
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 2A
AI summary
Methods and apparatuses for assembly of a non-planar device based on curved chips are described. Slots may be created as longitudinal openings in the chips to reduce bending stresses to increase allowable degrees of deformation of the chips. The chips may be deformed to a desired deformation within the allowable degrees of deformation via the slots. Holding constraints may be provided on at least a portion of the chips to allow the chips to remain curved according the desired deformation. A non-planner integrated circuit device comprising a flexible structure and at least one fixture structure bonded to the flexible structure is also described. The flexible structure may be curved in a desired deformation. A plurality of contact areas may be included in the flexible structure. Circuitry may be embedded within the flexible structure to perform processing operations.