Non-Planar Floating Gate Coupling Ratio Enhancement
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Solution Overview
Problem
As semiconductor memory cells are scaled, the dimensions of the capacitive coupling between the coupling gate and the floating gate decrease, leading to a reduction in the coupling ratio, which affects the memory cell's operational effectiveness without allowing for an increase in the size of the floating gate or coupling gate.
Innovation Solution
The floating gate and coupling gate are designed with non-planar upper and lower surfaces, respectively, where the upper surface of the floating gate and the lower surface of the coupling gate have a step-shaped contour, allowing for an increased coupling ratio without expanding the physical dimensions of the gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the memory cell is scaled down, then the device size is reduced, but the coupling ratio between the floating gate and coupling gate decreases
Solution Approach 1:
The patent introduces a non-planar, three-dimensional surface topology to the floating gate and coupling gate interfaces. By creating stepped or contoured surfaces that extend vertically and laterally, the design increases the effective coupling area without increasing the planar footprint of the device, thus maintaining coupling ratio during scaling.
Solution Approach 2:
The patent implements a nested structure where the coupling gate is positioned over and coupled to the floating gate in a vertically stacked arrangement. The non-planar surfaces create multiple levels of interaction between the gates, effectively nesting the coupling interface within the vertical dimension rather than requiring lateral expansion.
2Reliability
If the floating gate and coupling gate sizes are increased, then the coupling ratio is improved, but the device area increases
Solution Approach 1:
Instead of increasing gate dimensions in the planar direction, the patent utilizes the vertical dimension by creating non-planar surfaces with steps and contours. This allows the coupling interface to extend upward and create larger effective coupling area without increasing the lateral device footprint.
Solution Approach 2:
The patent applies non-planar surface features locally at the interface between the floating gate and coupling gate, rather than uniformly increasing all gate dimensions. The stepped or contoured surfaces are concentrated at the coupling interface where they maximize capacitive coupling without adding unnecessary device area elsewhere.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the coupling ratio between the floating gate and the coupling gate, maintaining effective memory cell operation even at smaller scales by ensuring consistent capacitive coupling, thereby supporting the continued functionality of the memory cell.
Implementation Method 1
the dimensions of the capacitive coupling between the coupling gate and the floating gate decrease, leading to a reduction in the coupling ratio
Implementation Method 2
a first positive voltage in the shape of a pulse is applied to the word line 20 causing the portion of the channel region 18 under the word line 20 to be conductive
Implementation Method 3
As they near the floating gate 24, they experience a sudden increase in the electric field caused by the voltage applied to the coupling gate 26 and the erase gate 28, causing the charges to be injected onto the floating gate 24. Thus, programming occurs through the mechanism of hot electron injection.
Implementation Method 4
Charges on the floating gate 24 are attracted to the erase gate 28 by tunneling through the insulating layer between the floating gate 24 and the erase gate 28. In particular, the floating gate 24 may be formed with a sharp tip facing the erase gate 28, thereby facilitating the Fowler-Nordheim tunneling of electrons from the floating gate 24
Data Source
AI summary
A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape. An array of such cells and a method of manufacturing the cells are also disclosed.