Non-Planar Gated Diode Source Region Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor gated diodes face issues with junction leakage and short channel effects due to high doping concentrations, which are exacerbated by their small size, leading to reduced performance and increased capacitance.
Innovation Solution
A semiconductor device with a non-planar source and drain configuration, where the upper boundary of the source and drain regions is raised or sloped relative to the gate structure, reducing dopant encroachment and lateral scattering, and allowing for a lower electric field and reduced junction leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high doping concentrations are used in small-sized gated diodes, then the device can function properly, but junction leakage and short channel effects increase
Solution Approach 1:
The source region is transformed from a planar two-dimensional structure to a three-dimensional non-planar structure with vertical extent. The source region extends upward from the substrate surface to a height that intersects the gate structure, creating a vertical dimension that allows dopant distribution to be controlled separately in vertical and lateral directions, thereby reducing lateral dopant encroachment while maintaining necessary vertical doping for device function
Solution Approach 2:
The doping concentration is made non-uniform within the source region by creating a vertical gradient. The dopant concentration is highest at the substrate interface and decreases toward the upper surface, allowing high doping where needed for device functionality at the junction interface while maintaining lower effective doping at the surface to reduce lateral scattering and junction leakage
2Reliability
If high doping concentrations are used in gated diodes, then electrical conduction is improved, but lateral scattering and dopant encroachment increase
Solution Approach 1:
The source region extends vertically to intersect the gate structure, separating the vertical conduction path from lateral dopant diffusion. This vertical extension allows electrical conduction to be maintained through the doped source region while the vertical geometry confines dopant distribution, reducing lateral scattering effects that would occur in a planar structure
Solution Approach 2:
A vertical dopant concentration gradient is established within the source region, with maximum doping at the substrate interface where vertical conduction is needed and decreasing concentration toward the surface. This local variation in doping quality maintains electrical conduction while minimizing lateral scattering
3Object-generated harmful factors
If the source region is made non-planar with vertical extent, then junction leakage is reduced, but device fabrication complexity increases
Solution Approach 1:
The non-planar source region geometry is established during the epitaxial growth or ion implantation process before subsequent fabrication steps. By pre-forming the vertical source structure with appropriate dopant distribution in early processing stages, the geometry is locked in before additional manufacturing complexity is introduced in later steps
Solution Approach 2:
The source region geometry is defined by controlling epitaxial growth parameters or ion implantation conditions to create the vertical extension. By adjusting growth temperature, time, or implantation energy and angle, the non-planar geometry is achieved through parameter optimization rather than complex multi-step fabrication processes
Data Source
AI summary
A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.