Non-Planar Interposer for Compact Semiconductor Stacking
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Solution Overview
Problem
Current semiconductor multi-chip packages face challenges in achieving compactness and efficiency due to limitations in packaging techniques, particularly in vertically stacking semiconductor chips, where interposers are used but do not effectively minimize thickness and prevent electrical shortages.
Innovation Solution
The use of interposers with non-planar top surfaces, featuring stepped regions with varying thicknesses, allows for the efficient stacking and electrical connection of semiconductor chips, reducing overall package thickness and preventing electrical contact issues through strategic placement and bonding wire management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional planar interposers are used in vertical stacking, then electrical connection is maintained, but package thickness is increased and compactness is reduced
Solution Approach 1:
The interposer is designed with non-uniform thickness, featuring a first region with greater thickness and a second region with lesser thickness. This local variation in quality allows the interposer to provide robust electrical connection support where needed while minimizing thickness in other areas, thereby resolving the contradiction between package compactness and electrical connection reliability.
Solution Approach 2:
The invention transitions from a conventional planar (2D) interposer to a three-dimensional non-planar interposer with varying thickness. This dimensional change enables the interposer to simultaneously achieve electrical connection reliability through its structured thickness variation and package compactness through reduced overall thickness, particularly in the second region.
2Reliability
If thicker interposers are used to ensure electrical connection, then electrical shortages are prevented, but device compactness and integration are reduced
Solution Approach 1:
The interposer implements local quality variation with a first region of greater thickness for enhanced electrical connection stability and a second region of lesser thickness for compactness. This localized differentiation allows the device to achieve high integration levels without compromising electrical connection reliability, as each region is optimized for its specific function.
Solution Approach 2:
The interposer is segmented into distinct regions (first region and second region) with different thickness characteristics. This segmentation allows independent optimization of each region - the first region ensures electrical connection stability while the second region enables compact packaging and high integration, thereby resolving the contradiction between reliability and device complexity.
3Volume of moving object
If uniform thickness interposers are used, then manufacturing is simplified, but electrical connection reliability and compactness cannot be simultaneously optimized
Solution Approach 1:
The interposer employs local quality variation with different thickness regions, which can be manufactured using standard semiconductor fabrication techniques such as selective etching or deposition. This approach allows simultaneous optimization of package thickness and electrical connection reliability without requiring fundamentally new manufacturing processes, thus maintaining ease of manufacture while achieving superior performance.
Data Source
AI summary
A semiconductor package and methods for manufacturing the same are provided. The semiconductor package includes a substrate, first and second semiconductor chips stacked on the substrate. An interposer is disposed between the first and second semiconductor chips. The interposer has a non-planar top surface.