Non-Planar MOSFET Cavity Gate Channel Length Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Lithographic limitations hinder the consistent and uniform definition of gate and source-drain channel lengths in MOSFETs, making it difficult to fabricate dense and complex integrated circuits.
Innovation Solution
Forming non-planar MOSFETs in cavities extending into the semiconductor substrate, where the gate insulator and channel region lie proximate to the cavity sidewall with an angle of at least 90 degrees, allowing the channel length to be determined by cavity depth rather than lithographic capabilities, enabling the formation of very short channels and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithographic capabilities are used to define gate and source-drain channel length, then manufacturing process is simple, but manufacturing precision deteriorates due to physical limitations
Solution Approach 1:
The patent transitions from planar (2D) gate structures to three-dimensional cavity structures extending into the substrate. The gate and channel length are defined by the cavity depth (vertical dimension) rather than by lateral lithographic patterns, thereby escaping lithographic resolution limits and achieving superior manufacturing precision for short channel lengths.
2Reliability
If planar MOSFET structures are used, then device fabrication is straightforward, but device performance deteriorates due to lithographic limitations
Solution Approach 1:
The invention moves from planar surface structures to vertical cavity structures extending into the substrate. This dimensional transition enables precise control of channel length through cavity depth, improving device performance by enabling very short channels while maintaining manufacturing feasibility through established etching and deposition techniques.
3Reliability
If very short channels are formed, then device performance improves, but manufacturing precision deteriorates due to lithographic limitations
Solution Approach 1:
By defining channel length through vertical cavity depth rather than lateral lithographic dimensions, the patent achieves manufacturing precision for very short channels that is independent of lithographic resolution limits. The cavity depth can be precisely controlled using standard semiconductor fabrication techniques.
Solution Approach 2:
The patent changes the controlling parameter for channel length from lateral dimensions (subject to lithographic limits) to vertical depth (controllable by etching processes). This parameter transformation enables precise definition of very short channel lengths with improved uniformity and repeatability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for consistent and precise control of channel length independent of lithographic limitations, enhancing manufacturing yield and enabling the construction of complex circuits with improved carrier mobility and reduced ON-resistance.
Implementation Method 1
The cavity sidewall (27) has an angle α with respect to the semiconductor surface (212) where α is desirably at least about 90 degrees and may be as much as or more than about 95 degrees. The channel length (30) depends on the bottom depth (51) of the cavity and the depth (241, 641) from the surface (212) of a source or drain region (24, 64, 68) adjacent the sidewall (27) of the cavity (50).
Implementation Method 2
The source and drain regions (22, 62 or 24, 64) are preferably formed epitaxially
Implementation Method 3
strain inducing materials can be used therein to improve channel carrier mobility and reduce ON-resistance
Data Source
AI summary
Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle α preferably about ≧90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.