Non-Planar Oxide Semiconductor TFTs for High-Density eDRAM Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional thin-film transistors (TFTs) face challenges in achieving high memory density and reducing off-state leakage, which limits their integration with advanced architectures and increases capacitor size, making them less efficient for applications like embedded dynamic random access memory (eDRAM).
Innovation Solution
The development of non-planar oxide semiconductor TFTs with a multi-gate architecture, using metal oxide channel materials like IGZO, which allows for lower off-state leakage and higher retention rates, enabling the integration of eDRAM within metal interconnect layers and reducing capacitor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar TFT architecture is used, then manufacturing process is simple, but memory density is low and off-state leakage is high
Solution Approach 1:
The patent transitions from conventional planar (2D) TFT architecture to a non-planar, vertically stacked 3D architecture. The channel extends vertically through multiple tiers with source and drain regions positioned at different heights, creating a three-dimensional conductive path that increases functional density without proportionally increasing planar footprint.
Solution Approach 2:
The patent implements a multi-tier stacked structure where multiple active tiers are nested vertically within a single device footprint. Each tier contains complete source-channel-drain configurations, and tiers are stacked one above another, allowing multiple transistor functions to be nested in a compact vertical arrangement.
2Reliability
If conventional planar TFT architecture is used, then device structure is simple, but off-state leakage is high
Solution Approach 1:
The vertical stacking architecture creates additional gate control surfaces that wrap around the channel from multiple directions (top, bottom, and sidewalls), providing superior electrostatic control over the conductive path. This multi-dimensional gating effectively suppresses off-state leakage by controlling carrier flow from all spatial directions.
Solution Approach 2:
The channel is segmented into multiple discrete tiers, each independently controlled by its own gate electrode. This segmentation allows each tier to be optimized for specific functions and enables independent control of conductive paths, improving overall device reliability and reducing leakage through distributed control.
3Adaptability or versatility
If conventional planar TFT architecture is used, then capacitor size is large, but integration with metal interconnect layers is limited
Solution Approach 1:
The vertical stacking architecture frees up planar space by moving transistor functions into the vertical dimension, enabling capacitors to be integrated within the same metal interconnect layers. The compact footprint allows capacitor electrodes to be positioned in previously unavailable vertical spaces between and around the stacked tiers.
Solution Approach 2:
The patent merges transistor and capacitor functions into a unified integrated structure where both components share the same metal interconnect layers and vertical space. The stacked transistor architecture and capacitor are combined in a single device footprint, enabling monolithic integration without requiring separate processing steps or additional layer stacks.
4Manufacturing precision
If conventional planar TFT architecture is used, then gate length variation is high, but manufacturing process is simple
Solution Approach 1:
By moving gate length definition into the vertical dimension through stacked tiers, the patent achieves more precise gate length control. The vertical stacking allows gate electrodes to be positioned at exact heights with controlled thicknesses, reducing variability compared to planar processes where gate length is defined by lateral lithographic dimensions that are more sensitive to process variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by reducing gate length variation and short channel effects, leading to higher memory density and lower off-state leakage, thus enabling more compact and efficient eDRAM arrays.
Implementation Method 1
the gate dielectric comprises a high-k dielectric material
Data Source
AI summary
Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.