Non-Planar Conductive Pillar for Semiconductor Solder Joint Integrity

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Solution Overview

Problem

Conventional semiconductor packaging technologies face challenges due to stress caused by differences in thermal expansion coefficients between layers, leading to cracks in solder joints between pillars and bump electrodes, which affects the structural integrity and reliability of chip-scale and ball grid array packages.

Innovation Solution

A conductive pillar with a non-planar top surface, such as concave, convex, or wave-shaped, is used, optionally capped with a material like nickel to enhance the inter-metallic compound layer, reducing stress and crack propagation by creating a stronger and more durable bonding interface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional planar pillar structures are used, then manufacturing is simple, but stress from thermal expansion differences causes cracks in solder joints

Engineering Contradiction:

Improvesolder joint integrityVSAvoidpillar surface geometry

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies curvature to the pillar top surface by forming it with a non-planar geometry (concave, convex, or wave-shaped). This curved surface design redistributes the thermal stress that arises from coefficient of thermal expansion differences between layers, preventing stress concentration at the solder joint interface and thereby improving solder joint integrity without requiring complex manufacturing processes

Inventive Principle:

Principle #14Spheroidality (Curvature)

2Reliability

If a non-planar pillar surface is used, then crack propagation is reduced, but manufacturing complexity increases

Engineering Contradiction:

Improveresistance to crack propagationVSAvoidpillar formation process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the geometric parameter of the pillar top surface from planar to non-planar (concave, convex, or wave-shaped). This parameter change in surface geometry provides crack propagation resistance by distributing stress more evenly, while the formation process remains compatible with standard semiconductor manufacturing techniques, thus maintaining ease of manufacture

Inventive Principle:

Principle #35Parameter changes

3Strength

If standard planar bonding interface is used, then manufacturing is straightforward, but thermal stress causes bonding failures

Engineering Contradiction:

Improvebonding interface strengthVSAvoidinterface geometry

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The patent introduces curvature to the bonding interface by forming the pillar top surface with a non-planar geometry. This curved interface design enhances bonding strength by distributing thermal stress from coefficient of thermal expansion differences across the entire interface area, preventing stress concentration and bonding failures, while the geometry can be achieved through standard fabrication processes

Inventive Principle:

Principle #14Spheroidality (Curvature)

Data Source

PatentUS8546945B2Pillar structure having a non-planar surface for semiconductor devices

Publication Date: 2013.10.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.